@@ -14,6 +14,8 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
@@ -35,6 +37,7 @@
#define SUN4I_CTL_CPHA BIT(2)
#define SUN4I_CTL_CPOL BIT(3)
#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
+#define SUN4I_CTL_DMAMC_DEDICATED BIT(5)
#define SUN4I_CTL_LMTF BIT(6)
#define SUN4I_CTL_TF_RST BIT(8)
#define SUN4I_CTL_RF_RST BIT(9)
@@ -52,6 +55,8 @@
#define SUN4I_INT_STA_REG 0x10
#define SUN4I_DMA_CTL_REG 0x14
+#define SUN4I_DMA_CTL_RF_READY BIT(0)
+#define SUN4I_DMA_CTL_TF_NOT_FULL BIT(10)
#define SUN4I_WAIT_REG 0x18
@@ -85,6 +90,9 @@ struct sun4i_spi {
const u8 *tx_buf;
u8 *rx_buf;
int len;
+
+ struct dma_chan *rx_dma_chan;
+ struct dma_chan *tx_dma_chan;
};
static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
@@ -131,6 +139,24 @@ static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
}
}
+static bool sun4i_spi_can_dma(struct spi_master *master,
+ struct spi_device *spi,
+ struct spi_transfer *tfr)
+{
+ return tfr->len >= SUN4I_FIFO_DEPTH;
+}
+
+static int sun4i_spi_prepare_message(struct spi_master *master,
+ struct spi_message *msg)
+{
+ struct sun4i_spi *sspi = spi_master_get_devdata(master);
+
+ master->dma_rx = sspi->rx_dma_chan;
+ master->dma_tx = sspi->tx_dma_chan;
+
+ return 0;
+}
+
static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
{
struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
@@ -170,6 +196,7 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
struct spi_transfer *tfr)
{
struct sun4i_spi *sspi = spi_master_get_devdata(master);
+ struct dma_async_tx_descriptor *desc_tx, *desc_rx;
unsigned int mclk_rate, div, timeout;
unsigned int tx_len = 0;
int ret = 0;
@@ -187,7 +214,6 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
/* Clear pending interrupts */
sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
-
reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
/* Reset FIFOs */
@@ -270,12 +296,55 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
- /* Fill the TX FIFO */
- sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
-
/* Enable the interrupts */
sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
+ if (sun4i_spi_can_dma(master, spi, tfr)) {
+ dev_dbg(&sspi->master->dev, "Using DMA mode for transfer\n");
+
+ if (sspi->tx_buf) {
+ desc_tx = dmaengine_prep_slave_sg(sspi->tx_dma_chan,
+ tfr->tx_sg.sgl, tfr->tx_sg.nents,
+ DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ if (!desc_tx) {
+ dev_err(&sspi->master->dev, "Couldn't prepare dma slave\n");
+ return -EIO;
+ }
+
+ dmaengine_submit(desc_tx);
+ }
+
+ if (sspi->rx_buf) {
+ desc_rx = dmaengine_prep_slave_sg(sspi->rx_dma_chan,
+ tfr->rx_sg.sgl, tfr->rx_sg.nents,
+ DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ if (!desc_rx) {
+ dev_err(&sspi->master->dev, "Couldn't prepare dma slave\n");
+ return -EIO;
+ }
+
+ dmaengine_submit(desc_rx);
+ }
+
+ /* Enable DMA requests */
+ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
+ sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_DMAMC_DEDICATED);
+ sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, SUN4I_DMA_CTL_TF_NOT_FULL | SUN4I_DMA_CTL_RF_READY);
+
+ dma_async_issue_pending(sspi->rx_dma_chan);
+ dma_async_issue_pending(sspi->tx_dma_chan);
+ } else {
+ dev_dbg(&sspi->master->dev, "Using PIO mode for transfer\n");
+
+ /* Disable DMA requests */
+ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
+ sun4i_spi_write(sspi, SUN4I_CTL_REG, reg & ~SUN4I_CTL_DMAMC_DEDICATED);
+ sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, 0);
+
+ /* Fill the TX FIFO */
+ sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
+ }
+
/* Start the transfer */
reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
@@ -287,7 +356,15 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
goto out;
}
- sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
+ if (sspi->tx_buf && sspi->rx_buf && sun4i_spi_can_dma(master, spi, tfr)) {
+ /* For some reason, doing this seems to crash and burn more
+ * often than not
+ * dma_wait_for_async_tx(desc_tx);
+ * dma_wait_for_async_tx(desc_rx);
+ */
+ } else {
+ sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
+ }
out:
sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
@@ -352,6 +429,7 @@ static int sun4i_spi_runtime_suspend(struct device *dev)
static int sun4i_spi_probe(struct platform_device *pdev)
{
+ struct dma_slave_config dma_sconfig;
struct spi_master *master;
struct sun4i_spi *sspi;
struct resource *res;
@@ -387,7 +465,10 @@ static int sun4i_spi_probe(struct platform_device *pdev)
goto err_free_master;
}
+ init_completion(&sspi->done);
sspi->master = master;
+ master->can_dma = sun4i_spi_can_dma;
+ master->prepare_message = sun4i_spi_prepare_message;
master->set_cs = sun4i_spi_set_cs;
master->transfer_one = sun4i_spi_transfer_one;
master->num_chipselect = 4;
@@ -410,7 +491,45 @@ static int sun4i_spi_probe(struct platform_device *pdev)
goto err_free_master;
}
- init_completion(&sspi->done);
+ sspi->tx_dma_chan = dma_request_slave_channel_reason(&pdev->dev, "tx");
+ if (IS_ERR(sspi->tx_dma_chan)) {
+ dev_err(&pdev->dev, "Unable to acquire DMA channel TX\n");
+ ret = PTR_ERR(sspi->tx_dma_chan);
+ goto err_free_master;
+ }
+
+ dma_sconfig.direction = DMA_MEM_TO_DEV;
+ dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ dma_sconfig.dst_addr = res->start + SUN4I_TXDATA_REG;
+ dma_sconfig.src_maxburst = 1;
+ dma_sconfig.dst_maxburst = 1;
+
+ ret = dmaengine_slave_config(sspi->tx_dma_chan, &dma_sconfig);
+ if (ret) {
+ dev_err(&pdev->dev, "Unable to configure TX DMA slave\n");
+ goto err_tx_dma_release;
+ }
+
+ sspi->rx_dma_chan = dma_request_slave_channel_reason(&pdev->dev, "rx");
+ if (IS_ERR(sspi->rx_dma_chan)) {
+ dev_err(&pdev->dev, "Unable to acquire DMA channel RX\n");
+ ret = PTR_ERR(sspi->rx_dma_chan);
+ goto err_tx_dma_release;
+ }
+
+ dma_sconfig.direction = DMA_DEV_TO_MEM;
+ dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ dma_sconfig.src_addr = res->start + SUN4I_RXDATA_REG;
+ dma_sconfig.src_maxburst = 1;
+ dma_sconfig.dst_maxburst = 1;
+
+ ret = dmaengine_slave_config(sspi->rx_dma_chan, &dma_sconfig);
+ if (ret) {
+ dev_err(&pdev->dev, "Unable to configure RX DMA slave\n");
+ goto err_rx_dma_release;
+ }
/*
* This wake-up/shutdown pattern is to be able to have the
@@ -419,7 +538,7 @@ static int sun4i_spi_probe(struct platform_device *pdev)
ret = sun4i_spi_runtime_resume(&pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Couldn't resume the device\n");
- goto err_free_master;
+ goto err_rx_dma_release;
}
pm_runtime_set_active(&pdev->dev);
@@ -437,6 +556,10 @@ static int sun4i_spi_probe(struct platform_device *pdev)
err_pm_disable:
pm_runtime_disable(&pdev->dev);
sun4i_spi_runtime_suspend(&pdev->dev);
+err_rx_dma_release:
+ dma_release_channel(sspi->rx_dma_chan);
+err_tx_dma_release:
+ dma_release_channel(sspi->tx_dma_chan);
err_free_master:
spi_master_put(master);
return ret;
@@ -444,8 +567,17 @@ err_free_master:
static int sun4i_spi_remove(struct platform_device *pdev)
{
+ struct spi_master *master = platform_get_drvdata(pdev);
+ struct sun4i_spi *sspi = spi_master_get_devdata(master);
+
+ if (pm_runtime_active(&pdev->dev))
+ sun4i_spi_runtime_suspend(&pdev->dev);
+
pm_runtime_disable(&pdev->dev);
+ dma_release_channel(sspi->rx_dma_chan);
+ dma_release_channel(sspi->tx_dma_chan);
+
return 0;
}
This patch adds DMA support for 64 byte transfers on the sun4i SPI controller. Bigger transfers did not seem to work when tested, and if the hardware actually supports those, it will need further investigation as to how to issue them correctly. Signed-off-by: Emilio López <emilio@elopez.com.ar> --- This is a straight adaptation of a similar patch Maxime made for the sun6i SPI driver. drivers/spi/spi-sun4i.c | 146 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 139 insertions(+), 7 deletions(-)