diff mbox

DaVinci: DM365: Fix Compilation issue due to PINMUX entry

Message ID 1249322304-12189-1-git-send-email-s-paulraj@ti.com (mailing list archive)
State Accepted
Headers show

Commit Message

s-paulraj@ti.com Aug. 3, 2009, 5:58 p.m. UTC 
From: Sandeep Paulraj <s-paulraj@ti.com>

The mask can hold only 8 bit values. This gave a
compilation warning. This patch rectifies the warning.


Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
---
 arch/arm/mach-davinci/dm365.c            |    3 ++-
 arch/arm/mach-davinci/include/mach/mux.h |    3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

Comments

Kieran Bingham Aug. 4, 2009, 8:04 a.m. UTC | #1 
s-paulraj@ti.com wrote:
> From: Sandeep Paulraj <s-paulraj@ti.com>
>
> The mask can hold only 8 bit values. This gave a
> compilation warning. This patch rectifies the warning.
>
>
> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
> ---
>  arch/arm/mach-davinci/dm365.c            |    3 ++-
>  arch/arm/mach-davinci/include/mach/mux.h |    3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
> index f02bce8..e648411 100644
> --- a/arch/arm/mach-davinci/dm365.c
> +++ b/arch/arm/mach-davinci/dm365.c
> @@ -582,7 +582,8 @@ MUX_CFG(DM365,	VOUT_COUTH_EN,	1,   8,     0xff, 0x55,  false)
>  MUX_CFG(DM365,	VIN_CAM_WEN,	0,   14,    3,	  0,	 false)
>  MUX_CFG(DM365,	VIN_CAM_VD,	0,   13,    1,	  0,	 false)
>  MUX_CFG(DM365,	VIN_CAM_HD,	0,   12,    1,	  0,	 false)
> -MUX_CFG(DM365,	VIN_YIN_EN,	0,   0,     0xfff, 0,	 false)
> +MUX_CFG(DM365,	VIN_YIN4_7_EN,	0,   0,     0xff, 0,	 false)
> +MUX_CFG(DM365,	VIN_YIN0_3_EN,	0,   8,     0xf,  0,	 false)
>   
Perhaps I'm wrong in following this, I haven't followed the macro back. 
I've just read the context of the lines above;
But would YIN0_3 not be the least significant bits, and YIN4_7 be the MSB's?
In which case shouldn't the 4_7 be set as 0xf and 0_3 be set as 0xff?

>  
>  INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
>  INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
> diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
> index 368fca6..a676b2f 100644
> --- a/arch/arm/mach-davinci/include/mach/mux.h
> +++ b/arch/arm/mach-davinci/include/mach/mux.h
> @@ -280,7 +280,8 @@ enum davinci_dm365_index {
>  	DM365_VIN_CAM_WEN,
>  	DM365_VIN_CAM_VD,
>  	DM365_VIN_CAM_HD,
> -	DM365_VIN_YIN_EN,
> +	DM365_VIN_YIN4_7_EN,
> +	DM365_VIN_YIN0_3_EN,
>  
>  	/* IRQ muxing */
>  	DM365_INT_EDMA_CC,
>   
Just pondering :)
--
Kieran
s-paulraj@ti.com Aug. 4, 2009, 12:58 p.m. UTC | #2 
> -----Original Message-----
> From: Kieran Bingham [mailto:kieranbingham@gmail.com]
> Sent: Tuesday, August 04, 2009 4:05 AM
> To: Paulraj, Sandeep
> Cc: davinci-linux-open-source@linux.davincidsp.com
> Subject: Re: [PATCH] DaVinci: DM365: Fix Compilation issue due to PINMUX
> entry
> 
> s-paulraj@ti.com wrote:
> > From: Sandeep Paulraj <s-paulraj@ti.com>
> >
> > The mask can hold only 8 bit values. This gave a
> > compilation warning. This patch rectifies the warning.
> >
> >
> > Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
> > ---
> >  arch/arm/mach-davinci/dm365.c            |    3 ++-
> >  arch/arm/mach-davinci/include/mach/mux.h |    3 ++-
> >  2 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-
> davinci/dm365.c
> > index f02bce8..e648411 100644
> > --- a/arch/arm/mach-davinci/dm365.c
> > +++ b/arch/arm/mach-davinci/dm365.c
> > @@ -582,7 +582,8 @@ MUX_CFG(DM365,	VOUT_COUTH_EN,	1,   8,
> 0xff, 0x55,  false)
> >  MUX_CFG(DM365,	VIN_CAM_WEN,	0,   14,    3,	  0,	 false)
> >  MUX_CFG(DM365,	VIN_CAM_VD,	0,   13,    1,	  0,	 false)
> >  MUX_CFG(DM365,	VIN_CAM_HD,	0,   12,    1,	  0,	 false)
> > -MUX_CFG(DM365,	VIN_YIN_EN,	0,   0,     0xfff, 0,	 false)
> > +MUX_CFG(DM365,	VIN_YIN4_7_EN,	0,   0,     0xff, 0,	 false)
> > +MUX_CFG(DM365,	VIN_YIN0_3_EN,	0,   8,     0xf,  0,	 false)
> >
> Perhaps I'm wrong in following this, I haven't followed the macro back.
> I've just read the context of the lines above;
> But would YIN0_3 not be the least significant bits, and YIN4_7 be the
> MSB's?
> In which case shouldn't the 4_7 be set as 0xf and 0_3 be set as 0xff?
[Sandeep] if you refer to http://focus.ti.com/lit/ug/sprufg5/sprufg5.pdf

Page 118. YIN 4 to YIN 7 are represented by the first 8 bits of PINMUX 0 and YIN 0 to YIN 3 are represented by bits 8 to 11 of PINMUX 0.
The macros represent this info from the PINMUX.
> 
> >
> >  INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
> >  INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
> > diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-
> davinci/include/mach/mux.h
> > index 368fca6..a676b2f 100644
> > --- a/arch/arm/mach-davinci/include/mach/mux.h
> > +++ b/arch/arm/mach-davinci/include/mach/mux.h
> > @@ -280,7 +280,8 @@ enum davinci_dm365_index {
> >  	DM365_VIN_CAM_WEN,
> >  	DM365_VIN_CAM_VD,
> >  	DM365_VIN_CAM_HD,
> > -	DM365_VIN_YIN_EN,
> > +	DM365_VIN_YIN4_7_EN,
> > +	DM365_VIN_YIN0_3_EN,
> >
> >  	/* IRQ muxing */
> >  	DM365_INT_EDMA_CC,
> >
> Just pondering :)
> --
> Kieran
Kevin Hilman Aug. 7, 2009, 11:43 p.m. UTC | #3 
s-paulraj@ti.com writes:

> From: Sandeep Paulraj <s-paulraj@ti.com>
>
> The mask can hold only 8 bit values. This gave a
> compilation warning. This patch rectifies the warning.
>
> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Thanks, pushing today.

Kevin

> ---
>  arch/arm/mach-davinci/dm365.c            |    3 ++-
>  arch/arm/mach-davinci/include/mach/mux.h |    3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
> index f02bce8..e648411 100644
> --- a/arch/arm/mach-davinci/dm365.c
> +++ b/arch/arm/mach-davinci/dm365.c
> @@ -582,7 +582,8 @@ MUX_CFG(DM365,	VOUT_COUTH_EN,	1,   8,     0xff, 0x55,  false)
>  MUX_CFG(DM365,	VIN_CAM_WEN,	0,   14,    3,	  0,	 false)
>  MUX_CFG(DM365,	VIN_CAM_VD,	0,   13,    1,	  0,	 false)
>  MUX_CFG(DM365,	VIN_CAM_HD,	0,   12,    1,	  0,	 false)
> -MUX_CFG(DM365,	VIN_YIN_EN,	0,   0,     0xfff, 0,	 false)
> +MUX_CFG(DM365,	VIN_YIN4_7_EN,	0,   0,     0xff, 0,	 false)
> +MUX_CFG(DM365,	VIN_YIN0_3_EN,	0,   8,     0xf,  0,	 false)
>  
>  INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
>  INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
> diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
> index 368fca6..a676b2f 100644
> --- a/arch/arm/mach-davinci/include/mach/mux.h
> +++ b/arch/arm/mach-davinci/include/mach/mux.h
> @@ -280,7 +280,8 @@ enum davinci_dm365_index {
>  	DM365_VIN_CAM_WEN,
>  	DM365_VIN_CAM_VD,
>  	DM365_VIN_CAM_HD,
> -	DM365_VIN_YIN_EN,
> +	DM365_VIN_YIN4_7_EN,
> +	DM365_VIN_YIN0_3_EN,
>  
>  	/* IRQ muxing */
>  	DM365_INT_EDMA_CC,
> -- 
> 1.6.0.4
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source@linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
diff mbox

Patch

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index f02bce8..e648411 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -582,7 +582,8 @@  MUX_CFG(DM365,	VOUT_COUTH_EN,	1,   8,     0xff, 0x55,  false)
 MUX_CFG(DM365,	VIN_CAM_WEN,	0,   14,    3,	  0,	 false)
 MUX_CFG(DM365,	VIN_CAM_VD,	0,   13,    1,	  0,	 false)
 MUX_CFG(DM365,	VIN_CAM_HD,	0,   12,    1,	  0,	 false)
-MUX_CFG(DM365,	VIN_YIN_EN,	0,   0,     0xfff, 0,	 false)
+MUX_CFG(DM365,	VIN_YIN4_7_EN,	0,   0,     0xff, 0,	 false)
+MUX_CFG(DM365,	VIN_YIN0_3_EN,	0,   8,     0xf,  0,	 false)
 
 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 368fca6..a676b2f 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -280,7 +280,8 @@  enum davinci_dm365_index {
 	DM365_VIN_CAM_WEN,
 	DM365_VIN_CAM_VD,
 	DM365_VIN_CAM_HD,
-	DM365_VIN_YIN_EN,
+	DM365_VIN_YIN4_7_EN,
+	DM365_VIN_YIN0_3_EN,
 
 	/* IRQ muxing */
 	DM365_INT_EDMA_CC,