| Message ID | 1404750730-22996-10-git-send-email-j.anaszewski@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 07/07/14 18:32, Jacek Anaszewski wrote: > Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Pawel Moll <pawel.moll@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> > Cc: Kumar Gala <galak@codeaurora.org> > Cc: devicetree@vger.kernel.org > --- > arch/arm/boot/dts/exynos3250.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi > index 3e678fa..351871a 100644 > --- a/arch/arm/boot/dts/exynos3250.dtsi > +++ b/arch/arm/boot/dts/exynos3250.dtsi > @@ -206,6 +206,18 @@ > interrupts = <0 240 0>; > }; > > + jpeg-codec@11830000 { > + compatible = "samsung,exynos3250-jpeg"; > + reg = <0x11830000 0x1000>; > + interrupts = <0 171 0>; > + clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; > + clock-names = "jpeg", "sclk-jpeg"; > + samsung,power-domain = <&pd_cam>; > + assigned-clock-parents = <&cmu CLK_MOUT_CAM_BLK &cmu CLK_DIV_MPLL_PRE>, > + <&cmu CLK_SCLK_JPEG &cmu>; > + assigned-clock-rates = <&cmu CLK_SCLK_JPEG 150000000>; There is no support for the assigned-clock-parents/assigned-clock-rates in mainline yet unfortunately. I would suggest removing these two properties for now. And please send this patch to relevant maintainer, i.e. Kukjin Kim. > + }; Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 3e678fa..351871a 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -206,6 +206,18 @@ interrupts = <0 240 0>; }; + jpeg-codec@11830000 { + compatible = "samsung,exynos3250-jpeg"; + reg = <0x11830000 0x1000>; + interrupts = <0 171 0>; + clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; + clock-names = "jpeg", "sclk-jpeg"; + samsung,power-domain = <&pd_cam>; + assigned-clock-parents = <&cmu CLK_MOUT_CAM_BLK &cmu CLK_DIV_MPLL_PRE>, + <&cmu CLK_SCLK_JPEG &cmu>; + assigned-clock-rates = <&cmu CLK_SCLK_JPEG 150000000>; + }; + mshc_0: mshc@12510000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12510000 0x1000>;