| Message ID | 1407113264-23426-2-git-send-email-ohaugan@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
Hi Olav, On Mon, Aug 04, 2014 at 01:47:43AM +0100, Olav Haugan wrote: > Stage-1 context bank does not have SMMU_CBn_TCR[SL0] field. SL0 field > is only applicable to stage-2 context banks. Ha, I actually noticed this last week but didn't get around to writing a a fix. Thanks for taking a look! > Signed-off-by: Olav Haugan <ohaugan@codeaurora.org> > --- > drivers/iommu/arm-smmu.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index ff6633d..a83ca6a 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -833,6 +833,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) > reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); > break; > } > + reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); > + I think this block is all predicated on smmu->version > 1, so we need something for stage2 CBs on SMMUv1 too. Will -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 8/4/2014 2:41 AM, Will Deacon wrote: > Hi Olav, > > On Mon, Aug 04, 2014 at 01:47:43AM +0100, Olav Haugan wrote: >> Stage-1 context bank does not have SMMU_CBn_TCR[SL0] field. SL0 field >> is only applicable to stage-2 context banks. > > Ha, I actually noticed this last week but didn't get around to writing a > a fix. Thanks for taking a look! > >> Signed-off-by: Olav Haugan <ohaugan@codeaurora.org> >> --- >> drivers/iommu/arm-smmu.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c >> index ff6633d..a83ca6a 100644 >> --- a/drivers/iommu/arm-smmu.c >> +++ b/drivers/iommu/arm-smmu.c >> @@ -833,6 +833,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) >> reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); >> break; >> } >> + reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); >> + > > I think this block is all predicated on smmu->version > 1, so we need > something for stage2 CBs on SMMUv1 too. Oh, I see. I will fix that. Olav
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index ff6633d..a83ca6a 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -833,6 +833,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); break; } + reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); + } else { reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT; } @@ -843,8 +845,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) reg |= TTBCR_EAE | (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | - (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) | - (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); + (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT); writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); /* MAIR0 (stage-1 only) */
Stage-1 context bank does not have SMMU_CBn_TCR[SL0] field. SL0 field is only applicable to stage-2 context banks. Signed-off-by: Olav Haugan <ohaugan@codeaurora.org> --- drivers/iommu/arm-smmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)