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[1/7] drm/i915/bdw: Always issue a force restore

Message ID 1407176119-5294-1-git-send-email-rodrigo.vivi@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Rodrigo Vivi Aug. 4, 2014, 6:15 p.m. UTC
From: Ben Widawsky <benjamin.widawsky@intel.com>

The PDPs seem to get screwed up otherwise, specifically PDP0. I am not
really clear why this is required, it just works with full PPGTT.

v2: Only do it for gen8, to limit regression potential

v3: Fix the bugzilla links

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78891
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Ben Widawsky Aug. 5, 2014, 1:20 a.m. UTC | #1
On Mon, Aug 04, 2014 at 11:15:13AM -0700, Rodrigo Vivi wrote:
> From: Ben Widawsky <benjamin.widawsky@intel.com>
> 
> The PDPs seem to get screwed up otherwise, specifically PDP0. I am not
> really clear why this is required, it just works with full PPGTT.
> 
> v2: Only do it for gen8, to limit regression potential
> 
> v3: Fix the bugzilla links
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78891
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Hi Rodrigo. This patch  was superseded by my [partially merged] series
here:
http://lists.freedesktop.org/archives/intel-gfx/2014-July/048311.html

In that series I went through very thoroughly with design why we need to
do this, and verified those patches do address this issue.

So yeah, NAK from me - and please get those reworked or merged or
whatever.

Thanks

[snip]
Daniel Vetter Aug. 5, 2014, 8:41 a.m. UTC | #2
On Mon, Aug 04, 2014 at 06:20:00PM -0700, Ben Widawsky wrote:
> On Mon, Aug 04, 2014 at 11:15:13AM -0700, Rodrigo Vivi wrote:
> > From: Ben Widawsky <benjamin.widawsky@intel.com>
> > 
> > The PDPs seem to get screwed up otherwise, specifically PDP0. I am not
> > really clear why this is required, it just works with full PPGTT.
> > 
> > v2: Only do it for gen8, to limit regression potential
> > 
> > v3: Fix the bugzilla links
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78891
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938
> > 
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> Hi Rodrigo. This patch  was superseded by my [partially merged] series
> here:
> http://lists.freedesktop.org/archives/intel-gfx/2014-July/048311.html
> 
> In that series I went through very thoroughly with design why we need to
> do this, and verified those patches do address this issue.
> 
> So yeah, NAK from me - and please get those reworked or merged or
> whatever.

Iirc I've stopped merging on that series since it mixes up gen8 specific
fixes with generic ppgtt fixes. Specifically for the ppgtt_release issues
we now have a patch (plus fixups) which is almost ready (just stalling for
review). Can you pls go through that series with Rodrigo so that he knows
which parts are the gen8 fixes?

Thanks, Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 3b99390..56f7b1e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -586,6 +586,9 @@  mi_set_context(struct intel_engine_cs *ring,
 	else
 		intel_ring_emit(ring, MI_NOOP);
 
+	if (INTEL_INFO(ring->dev)->gen == 8)
+		hw_flags |= MI_FORCE_RESTORE;
+
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_emit(ring, MI_SET_CONTEXT);
 	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) |