| Message ID | 1407250286-1801-16-git-send-email-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Aug 05, 2014 at 07:51:26AM -0700, Rodrigo Vivi wrote: > From: Deepak S <deepak.s@linux.intel.com> > > Higher RC6 residency is observed using timeout mode > instead of EI mode. It's Recommended to use TO Method for RC6. > [TOR:] When I made the similar change for BDW, I understood timeout mode will provide benefit on some pre-production CHV steppings and no benefit on the production CHV steppings. Is that understanding still correct? Do we want to merge a change that is not expected to benefit any production steppings? > Signed-off-by: Deepak S <deepak.s@linux.intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index d3085b7..0cc8460 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4083,7 +4083,7 @@ static void cherryview_enable_rps(struct drm_device *dev) > I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); > I915_WRITE(GEN6_RC_SLEEP, 0); > > - I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ > + I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); [TOR:] A comment to explain the meaning of 0x557 could be helpful. > > /* allows RC6 residency counter to work */ > I915_WRITE(VLV_COUNTER_CONTROL, > @@ -4099,7 +4099,7 @@ static void cherryview_enable_rps(struct drm_device *dev) > /* 3: Enable RC6 */ > if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && > (pcbr >> VLV_PCBR_ADDR_SHIFT)) > - rc6_mode = GEN6_RC_CTL_EI_MODE(1); > + rc6_mode = GEN7_RC_CTL_TO_MODE; > > I915_WRITE(GEN6_RC_CONTROL, rc6_mode); > [TOR:] If we want to change from EI mode to TO mode for CHV, this patch does that correctly.
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d3085b7..0cc8460 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4083,7 +4083,7 @@ static void cherryview_enable_rps(struct drm_device *dev) I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); I915_WRITE(GEN6_RC_SLEEP, 0); - I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ + I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); /* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL, @@ -4099,7 +4099,7 @@ static void cherryview_enable_rps(struct drm_device *dev) /* 3: Enable RC6 */ if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && (pcbr >> VLV_PCBR_ADDR_SHIFT)) - rc6_mode = GEN6_RC_CTL_EI_MODE(1); + rc6_mode = GEN7_RC_CTL_TO_MODE; I915_WRITE(GEN6_RC_CONTROL, rc6_mode);