| Message ID | 1407404095-3265-4-git-send-email-kever.yang@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Kever, On Thu, Aug 7, 2014 at 2:34 AM, Kever Yang <kever.yang@rock-chips.com> wrote: > rk3288 has two kind of usb controller, this add the dwc2 controller > for otg and host1. > > Controller can works with usb PHY default setting and Vbus on. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > > --- > > Changes in v4: None > Changes in v3: > - EHCI and HSIC move new for version 3. > > Changes in v2: None > > arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) This looks good to me. I haven't been able to personally test the OTG port (since my board doesn't have vbus wired), but I've tested the Host port. I would request that you re-sort by base address (ignoring uart2, which apparently is in the wrong place). Please make sure you base atop my patch that fixes the sort order of OHCI and EHCI. I think that's supposed to land any day now. After changing the sort order: Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org>
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index e7cb008..9713054 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -156,6 +156,26 @@ status = "disabled"; }; + usb_host1: usb@ff540000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0xff540000 0x40000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_USBHOST1>; + clock-names = "otg"; + status = "disabled"; + }; + + usb_otg: usb@ff580000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0xff580000 0x40000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + status = "disabled"; + }; + uart2: serial@ff690000 { compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; reg = <0xff690000 0x100>;
rk3288 has two kind of usb controller, this add the dwc2 controller for otg and host1. Controller can works with usb PHY default setting and Vbus on. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> --- Changes in v4: None Changes in v3: - EHCI and HSIC move new for version 3. Changes in v2: None arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)