[v2,0/6] Add support of two Audio PLL source

Message

Shengjiu Wang July 1, 2022, 9:32 a.m. UTC

i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being
configured to handle 8kHz and 11kHz series audio rates.

The patches implement the functionality to select at runtime
the appropriate AUDIO PLL for root clock, if there is no
two PLL registered, then no action taken.

change in v2:
- simply the logic for calling reparent function

Shengjiu Wang (6):
  ASoC: fsl_utils: Add function to handle PLL clock source
  ASoC: fsl_spdif: Add support for PLL switch at runtime.
  ASoC: fsl_micfil: Add support for PLL switch at runtime
  ASoC: fsl_sai: Add support for PLL switch at runtime
  ASoC: dt-bindings: fsl_spdif: Add two PLL clock source
  ASoC: dt-bindings: fsl-sai: Add two PLL clock source

 .../devicetree/bindings/sound/fsl,spdif.yaml  |  4 ++
 .../devicetree/bindings/sound/fsl-sai.txt     |  3 +
 sound/soc/fsl/Kconfig                         |  3 +
 sound/soc/fsl/fsl_micfil.c                    | 31 +++++++++
 sound/soc/fsl/fsl_sai.c                       | 38 ++++++++++
 sound/soc/fsl/fsl_sai.h                       |  2 +
 sound/soc/fsl/fsl_spdif.c                     | 48 +++++++++++--
 sound/soc/fsl/fsl_utils.c                     | 69 +++++++++++++++++++
 sound/soc/fsl/fsl_utils.h                     |  7 ++
 9 files changed, 200 insertions(+), 5 deletions(-)

Comments

Mark Brown July 6, 2022, 11:07 a.m. UTC | #1

On Fri, 1 Jul 2022 17:32:35 +0800, Shengjiu Wang wrote:
> i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being
> configured to handle 8kHz and 11kHz series audio rates.
> 
> The patches implement the functionality to select at runtime
> the appropriate AUDIO PLL for root clock, if there is no
> two PLL registered, then no action taken.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/6] ASoC: fsl_utils: Add function to handle PLL clock source
      commit: 7bad8125549cda14d9ccf97d7d76f7ef6ac9d206
[2/6] ASoC: fsl_spdif: Add support for PLL switch at runtime.
      commit: 34dcdebecf2f05e1b275e1da8352f8e4c1aab6f6
[3/6] ASoC: fsl_micfil: Add support for PLL switch at runtime
      commit: 93f54100fbdedc22e8d88d037a8a3e32101724eb
[4/6] ASoC: fsl_sai: Add support for PLL switch at runtime
      commit: 7cb7f07d2491a3435578ab97eeeb70fadac6385c
[5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source
      commit: df0835a810c1585bd54ffb10db92b455e922c7ec
[6/6] ASoC: dt-bindings: fsl-sai: Add two PLL clock source
      commit: 6c06ad34eda9e1990313ff80999e1a75a02fa1c0

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark