From patchwork Fri Nov 16 13:41:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 10686371 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF7F61747 for ; Fri, 16 Nov 2018 13:40:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CD52F2CF5F for ; Fri, 16 Nov 2018 13:40:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C14902CF67; Fri, 16 Nov 2018 13:40:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC31A2CF50 for ; Fri, 16 Nov 2018 13:40:39 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id B080F2679C0; Fri, 16 Nov 2018 14:40:38 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 0F067267AFC; Fri, 16 Nov 2018 14:40:35 +0100 (CET) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by alsa0.perex.cz (Postfix) with ESMTP id 1B457267949 for ; Fri, 16 Nov 2018 14:40:32 +0100 (CET) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAGDeV4Y080949; Fri, 16 Nov 2018 07:40:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1542375631; bh=D57MtcRMcMYoKwYPIkdseLllmZ26OhyEhcNVjT92Lm4=; h=From:To:CC:Subject:Date; b=VNiugxc2lC43sgemlzC4FZkLXdyhy8MP5tVjtr5k/GGnfOebMNNtmCOxU7ULO3eIJ I5fbX5RyVJpHlvYZLmBPk7Du82cjeZhXqc9fzXEsuN3TyeDjuN6R9IvvACivMFebSI oTPUrSK06XwJFeszFjoKuDoYFRnW27pePVwiiMHo= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAGDeVtt057396 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 Nov 2018 07:40:31 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Fri, 16 Nov 2018 07:40:30 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Fri, 16 Nov 2018 07:40:30 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAGDeQwq005228; Fri, 16 Nov 2018 07:40:27 -0600 From: Peter Ujfalusi To: Mark Brown , Liam Girdwood Date: Fri, 16 Nov 2018 15:41:37 +0200 Message-ID: <20181116134141.17396-1-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, jsarha@ti.com, robh+dt@kernel.org, misael.lopez@ti.com Subject: [alsa-devel] [PATCH 0/4] ASoC; davinci-mcasp: Pin handling updates X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Hi, The series will improve the McASP pin handling: - To avoid non configured clocks leaking out from McASP - make sure that the AXR pin (TX) state is correct in all scenarios - Allow user configurable DISMOD for the tx pin instead of hardwiring it in the code to low The DISMOD configuration is needed when the codec requires the TX line to be high during inactive slots (mu-law codecs for example). Regards, Peter --- Peter Ujfalusi (4): ASoC: davinci-mcasp: Clear TXSTAT register before activating serializers ASoC: davinci-mcasp: Update PDIR (pin direction) register handling bindings: sound: davinci-mcasp: Document dismod optional property ASoC: davinci-mcasp: Implement configurable dismod handling .../bindings/sound/davinci-mcasp-audio.txt | 5 + include/linux/platform_data/davinci_asp.h | 1 + sound/soc/davinci/davinci-mcasp.c | 109 +++++++++++++++--- sound/soc/davinci/davinci-mcasp.h | 30 ++--- 4 files changed, 112 insertions(+), 33 deletions(-)