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Wed, 29 May 2024 18:33:56 +0200 Received: from pc49102-2217.se.axis.com (pc49102-2217.se.axis.com [10.88.7.5]) by se-intmail01x.se.axis.com (Postfix) with ESMTP id 353C5583; Wed, 29 May 2024 18:33:56 +0200 (CEST) Received: by pc49102-2217.se.axis.com (Postfix, from userid 9470) id 30965666EA08; Wed, 29 May 2024 18:33:56 +0200 (CEST) From: Ricard Wanderlof Subject: [PATCH 0/2] tlv320adc3xxx: Allow MICBIAS pins to be used as GPOs Date: Wed, 29 May 2024 18:33:43 +0200 Message-ID: <20240529-tlv320adc3xxx-micbias-gpo-v1-0-300d39cecc55@axis.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAOdYV2YC/x3MywqAIBBA0V+JWTdgaiH9SrTwMdVALzRCiP49a XkW9z6QKDIl6KsHIt2c+NgLmroCv9h9JuRQDFJILVpp8FpvJYUNXuWccWPv2CaczwOdcTo03ug uKCj9GWni/L+H8X0/Oes+NmsAAAA= To: Mark Brown , Liam Girdwood , Shenghao Ding , Kevin Lu , Baojun Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ricard Wanderlof , Jaroslav Kysela , Takashi Iwai CC: , , , , "Ricard Wanderlof" , X-Mailer: b4 0.13.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM1PEPF000252E0:EE_|DU2PR02MB10159:EE_ X-MS-Office365-Filtering-Correlation-Id: 12169276-c0dc-4f41-365f-08dc7ffd2365 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|376005|82310400017|1800799015|7416005|921011; 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X-OriginatorOrg: axis.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2024 16:33:57.6744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 12169276-c0dc-4f41-365f-08dc7ffd2365 X-MS-Exchange-CrossTenant-Id: 78703d3c-b907-432f-b066-88f7af9ca3af X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=78703d3c-b907-432f-b066-88f7af9ca3af;Ip=[195.60.68.100];Helo=[mail.axis.com] X-MS-Exchange-CrossTenant-AuthSource: AM1PEPF000252E0.eurprd07.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR02MB10159 In some cases, depending on system design, the MICBIAS pins on the chip are not needed as such, but a couple of extra GPIO pins would be useful. This patch allows the MICBIAS pins to be configured in the device tree as general purpose output pins, controlled via the GPIO framework. Owing to their originally intended purpose there are some limitations: when the MICBIAS pins are deactivated, they will float, so will likely need a pulldown in many applications. When activated, they will assume the voltage specified by the micbias1-vg and micbias2-vg properties, respectively, meaning that the resulting output voltage will be 2.0 V, 2.5 V or AVDD . Signed-off-by: Ricard Wanderlof --- Ricard Wanderlof (2): ASoC: dt-bindings: tlv320adc3xxx: Add MICBIAS-as-GPO properties tlv320adc3xxx: Add support for using MICBIAS pins as GPO .../bindings/sound/ti,tlv320adc3xxx.yaml | 20 ++++ sound/soc/codecs/tlv320adc3xxx.c | 105 ++++++++++++++++----- 2 files changed, 104 insertions(+), 21 deletions(-) --- base-commit: 47d09270d7776e46858a161f94b735640b2fb056 change-id: 20240528-tlv320adc3xxx-micbias-gpo-b8b4d1c846d3 Best regards,