diff mbox

[3/6] ASoC: rt5640: Remove the unused or incorrect setting of clock source

Message ID 1396009710-21324-3-git-send-email-oder_chiou@realtek.com (mailing list archive)
State Accepted
Commit acf04e639bba2270fd07e161fa984234591ef43b
Headers show

Commit Message

Oder Chiou March 28, 2014, 12:28 p.m. UTC 
The patch removes the unused or incorrect setting of clock source.

Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
---
 sound/soc/codecs/rt5640.c | 8 +-------
 sound/soc/codecs/rt5640.h | 2 --
 2 files changed, 1 insertion(+), 9 deletions(-)

Comments

Mark Brown March 28, 2014, 12:53 p.m. UTC | #1 
On Fri, Mar 28, 2014 at 08:28:27PM +0800, Oder Chiou wrote:
> The patch removes the unused or incorrect setting of clock source.

Applied, thanks.
diff mbox

Patch

diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c
index 2afce49..096edfe 100644
--- a/sound/soc/codecs/rt5640.c
+++ b/sound/soc/codecs/rt5640.c
@@ -487,7 +487,7 @@  static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
 
 	val = snd_soc_read(source->codec, RT5640_GLB_CLK);
 	val &= RT5640_SCLK_SRC_MASK;
-	if (val == RT5640_SCLK_SRC_PLL1 || val == RT5640_SCLK_SRC_PLL1T)
+	if (val == RT5640_SCLK_SRC_PLL1)
 		return 1;
 	else
 		return 0;
@@ -1694,12 +1694,6 @@  static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
 	case RT5640_SCLK_S_PLL1:
 		reg_val |= RT5640_SCLK_SRC_PLL1;
 		break;
-	case RT5640_SCLK_S_PLL1_TK:
-		reg_val |= RT5640_SCLK_SRC_PLL1T;
-		break;
-	case RT5640_SCLK_S_RCCLK:
-		reg_val |= RT5640_SCLK_SRC_RCCLK;
-		break;
 	default:
 		dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
 		return -EINVAL;
diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h
index 5e8df25a..cbd07b5 100644
--- a/sound/soc/codecs/rt5640.h
+++ b/sound/soc/codecs/rt5640.h
@@ -976,8 +976,6 @@ 
 #define RT5640_SCLK_SRC_SFT			14
 #define RT5640_SCLK_SRC_MCLK			(0x0 << 14)
 #define RT5640_SCLK_SRC_PLL1			(0x1 << 14)
-#define RT5640_SCLK_SRC_PLL1T			(0x2 << 14)
-#define RT5640_SCLK_SRC_RCCLK			(0x3 << 14) /* 15MHz */
 #define RT5640_PLL1_SRC_MASK			(0x3 << 12)
 #define RT5640_PLL1_SRC_SFT			12
 #define RT5640_PLL1_SRC_MCLK			(0x0 << 12)