From patchwork Tue Apr 28 12:43:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lin, Mengdong" X-Patchwork-Id: 6288531 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id ACF4FBEEE1 for ; Tue, 28 Apr 2015 12:33:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D5D4220374 for ; Tue, 28 Apr 2015 12:33:51 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 4D81120306 for ; Tue, 28 Apr 2015 12:33:50 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 7B16C26063D; Tue, 28 Apr 2015 14:33:49 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id B77662610A3; Tue, 28 Apr 2015 14:33:09 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id E85F02610A3; Tue, 28 Apr 2015 14:33:08 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by alsa0.perex.cz (Postfix) with ESMTP id 79F2F26129B for ; Tue, 28 Apr 2015 14:32:47 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 28 Apr 2015 05:32:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,663,1422950400"; d="scan'208";a="717070488" Received: from amanda-hsw-pc.sh.intel.com ([10.239.159.28]) by fmsmga002.fm.intel.com with ESMTP; 28 Apr 2015 05:32:25 -0700 From: mengdong.lin@intel.com To: alsa-devel@alsa-project.org, tiwai@suse.de Date: Tue, 28 Apr 2015 20:43:10 +0800 Message-Id: <1430224990-22229-1-git-send-email-mengdong.lin@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <4530387c0b63ccfafb5dbb3399a39b4093651c48.1429880424.git.mengdong.lin@intel.com> References: <4530387c0b63ccfafb5dbb3399a39b4093651c48.1429880424.git.mengdong.lin@intel.com> Cc: Mengdong Lin Subject: [alsa-devel] [PATCH v2 2/3] ALSA: hda - remove controller dependency on i915 power well for Baytrail/Braswell X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mengdong Lin For Baytrail (Valleyview) and Braswell (Cherryview), not the HD-A controller but only the display codec is in the shared power well with gfx. Signed-off-by: Mengdong Lin diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 1b688ba..e73dc34 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -1903,8 +1903,9 @@ static int azx_probe_continue(struct azx *chip) * display codec needs the power and it can be released after probe. */ if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { - /* Assume the controller needs the power by default */ - chip->need_i915_power = 1; + /* Baytral/Braswell controllers don't need this power */ + if (pci->device != 0x0f04 && pci->device != 0x2284) + chip->need_i915_power = 1; #ifdef CONFIG_SND_HDA_I915 err = hda_i915_init(hda); diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index 5f44f60..7b2744c 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -2335,6 +2335,14 @@ static int patch_generic_hdmi(struct hda_codec *codec) intel_haswell_fixup_enable_dp12(codec); } + /* For Valleyview/Cherryview, the codec is in the display power well. + * For Haswell/Broadwell, the controller is also in the power well and + * can cover codec power request, and so need not set this flag. + * For previous platforms, there is no such power well feature. + */ + if (is_valleyview_plus(codec)) + codec->core.need_i915_power = 1; + if (is_haswell_plus(codec) || is_valleyview_plus(codec)) codec->depop_delay = 0;