From patchwork Wed May 13 12:00:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 6396441 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2BEA99F1C2 for ; Wed, 13 May 2015 12:04:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 244992041C for ; Wed, 13 May 2015 12:04:37 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 8C69A20381 for ; Wed, 13 May 2015 12:04:32 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 579522660F8; Wed, 13 May 2015 14:04:31 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 7E1542661B5; Wed, 13 May 2015 14:02:31 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 36718265CC8; Wed, 13 May 2015 14:02:30 +0200 (CEST) Received: from mail-wi0-f179.google.com (mail-wi0-f179.google.com [209.85.212.179]) by alsa0.perex.cz (Postfix) with ESMTP id AB147265ABD for ; Wed, 13 May 2015 14:00:56 +0200 (CEST) Received: by widdi4 with SMTP id di4so52673562wid.0 for ; Wed, 13 May 2015 05:00:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=captVGSkUdXlgRcAJXidT2g3xy/aEzoz0fMtYVSnBMQ=; b=mpof+4RO4Q24z8PJyTWMWu9g8aav5V/5ZhzI2bTSwy/YpYVy4J5+jg2KiftT55qFn0 57coOB9J0snBcnzfYUfr86TZhOj4NtZJ5a0FpaN3VNa2bd2rd4exJCSvykZPW6TQTlkf fvgrExxxOPC52yp4V/yJ1gRvXY9QTC+5OkYJSNOWKuwoiThYVb7SZ00gfb0lqojCbXot eFpT6J5par+1jB6OvW8rmsOFVBFnBMT3aKhU4NuPUrXbA8DiU0Kkx4S0bA9WOix6uXqv vcB7bSaNjv0T8bY0Xc4BN17FJWmVbr0NFYRKEwc4H8/YmbWiD/2Of3axHDkTz2esodrV 6ZFA== X-Gm-Message-State: ALoCoQnel0NYq3Pq+04FoQ+8h5BX6CeGONex/YlX+DGA2lX29B4eDF71Vwk/J9mpiPo60jK1BVCv X-Received: by 10.181.11.193 with SMTP id ek1mr13848022wid.15.1431518456319; Wed, 13 May 2015 05:00:56 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-144-121-184.as13285.net. [78.144.121.184]) by mx.google.com with ESMTPSA id uc9sm14006618wjc.7.2015.05.13.05.00.54 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 May 2015 05:00:55 -0700 (PDT) From: Srinivas Kandagatla To: Patrick Lai , Mark Brown Date: Wed, 13 May 2015 13:00:52 +0100 Message-Id: <1431518452-7434-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431518302-7139-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1431518302-7139-1-git-send-email-srinivas.kandagatla@linaro.org> Cc: devicetree@vger.kernel.org, Kenneth Westfield , Banajit Goswami , Pawel Moll , Ian Campbell , Takashi Iwai , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Liam Girdwood , Rob Herring , Srinivas Kandagatla , Kumar Gala , alsa-devel@alsa-project.org Subject: [alsa-devel] [PATCH v1 05/13] ASoC: qcom: support bitclk and osrclk per i2s port X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support to allow bitclk and osrclk per i2s dai port. on APQ8016 there are 4 i2s ports each one has its own bit clks. Without this patch its not possible to support multiple i2s ports in the lpass driver. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/lpass-cpu.c | 54 ++++++++++++++++++++++++++++++---------------- sound/soc/qcom/lpass.h | 5 +++-- 2 files changed, 39 insertions(+), 20 deletions(-) diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 5965667..0d28ea7 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -33,7 +33,7 @@ static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); int ret; - ret = clk_set_rate(drvdata->mi2s_osr_clk, freq); + ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); if (ret) dev_err(dai->dev, "%s() error setting mi2s osrclk to %u: %d\n", __func__, freq, ret); @@ -47,18 +47,18 @@ static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); int ret; - ret = clk_prepare_enable(drvdata->mi2s_osr_clk); + ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->diver->id]); if (ret) { dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n", __func__, ret); return ret; } - ret = clk_prepare_enable(drvdata->mi2s_bit_clk); + ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->driver->id]); if (ret) { dev_err(dai->dev, "%s() error in enabling mi2s bit clk: %d\n", __func__, ret); - clk_disable_unprepare(drvdata->mi2s_osr_clk); + clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); return ret; } @@ -70,8 +70,8 @@ static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, { struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); - clk_disable_unprepare(drvdata->mi2s_bit_clk); - clk_disable_unprepare(drvdata->mi2s_osr_clk); + clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); + clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); } static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, @@ -146,7 +146,8 @@ static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, return ret; } - ret = clk_set_rate(drvdata->mi2s_bit_clk, rate * bitwidth * 2); + ret = clk_set_rate(drvdata->mi2s_bit_clk[dai->driver->id], + rate * bitwidth * 2); if (ret) { dev_err(dai->dev, "%s() error setting mi2s bitclk to %u: %d\n", __func__, rate * bitwidth * 2, ret); @@ -354,7 +355,8 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) struct lpass_variant *variant; struct device *dev = &pdev->dev; const struct of_device_id *match; - int ret; + char clk_name[16]; + int ret, i; dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); if (dsp_of_node) { @@ -400,18 +402,34 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) if (variant->init) variant->init(pdev); - drvdata->mi2s_osr_clk = devm_clk_get(&pdev->dev, "mi2s-osr-clk"); - if (IS_ERR(drvdata->mi2s_osr_clk)) { - dev_err(&pdev->dev, "%s() error getting mi2s-osr-clk: %ld\n", - __func__, PTR_ERR(drvdata->mi2s_osr_clk)); - return PTR_ERR(drvdata->mi2s_osr_clk); + for (i = 0; i < variant->num_dai; i++) { + if (variant->num_dai > 1) + sprintf(clk_name, "mi2s-osr-clk%d", i); + else + sprintf(clk_name, "mi2s-osr-clk"); + + drvdata->mi2s_osr_clk[i] = devm_clk_get(&pdev->dev, clk_name); + if (IS_ERR(drvdata->mi2s_osr_clk[i])) { + dev_err(&pdev->dev, "%s() error getting mi2s-osr-clk: %ld\n", + __func__, PTR_ERR(drvdata->mi2s_osr_clk[i])); + return PTR_ERR(drvdata->mi2s_osr_clk[i]); + } } - drvdata->mi2s_bit_clk = devm_clk_get(&pdev->dev, "mi2s-bit-clk"); - if (IS_ERR(drvdata->mi2s_bit_clk)) { - dev_err(&pdev->dev, "%s() error getting mi2s-bit-clk: %ld\n", - __func__, PTR_ERR(drvdata->mi2s_bit_clk)); - return PTR_ERR(drvdata->mi2s_bit_clk); + for (i = 0; i < variant->num_dai; i++) { + + if (variant->num_dai > 1) + sprintf(clk_name, "mi2s-bit-clk%d", i); + else + sprintf(clk_name, "mi2s-bit-clk"); + + drvdata->mi2s_bit_clk[i] = devm_clk_get(&pdev->dev, clk_name); + if (IS_ERR(drvdata->mi2s_bit_clk[i])) { + dev_err(&pdev->dev, + "%s() error getting mi2s-bit-clk: %ld\n", + __func__, PTR_ERR(drvdata->mi2s_bit_clk[i])); + return PTR_ERR(drvdata->mi2s_bit_clk[i]); + } } drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix-clk"); diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index caaf17f..75e9370 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -22,6 +22,7 @@ #include #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 +#define LPASS_MAX_MI2S_PORTS (8) /* Both the CPU DAI and platform drivers will access this data */ struct lpass_data { @@ -30,10 +31,10 @@ struct lpass_data { struct clk *ahbix_clk; /* MI2S system clock */ - struct clk *mi2s_osr_clk; + struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS]; /* MI2S bit clock (derived from system clock by a divider */ - struct clk *mi2s_bit_clk; + struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS]; /* low-power audio interface (LPAIF) registers */ void __iomem *lpaif;