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[59.115.240.142]) by smtp.gmail.com with ESMTPSA id fw15sm4389856pdb.26.2015.08.11.20.09.41 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Aug 2015 20:09:42 -0700 (PDT) Message-ID: <1439348979.3594.4.camel@ingics.com> From: Axel Lin To: Mark Brown Date: Wed, 12 Aug 2015 11:09:39 +0800 In-Reply-To: <1439348866.3594.2.camel@ingics.com> References: <1439348866.3594.2.camel@ingics.com> X-Mailer: Evolution 3.12.10-0ubuntu1~14.10.1 Mime-Version: 1.0 Cc: Brian Austin , alsa-devel@alsa-project.org, Liam Girdwood , Paul Handrigan Subject: [alsa-devel] [PATCH 3/4] ASoC: cs42l56: Use case range at appropriate place X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP The readable registers are in continuous range: 0x01 ~ 0x2e. Use case range syntax makes the code shorter with better readability when we have a large number of continuous switch cases. No functional change with this patch. Signed-off-by: Axel Lin --- sound/soc/codecs/cs42l56.c | 47 +--------------------------------------------- 1 file changed, 1 insertion(+), 46 deletions(-) diff --git a/sound/soc/codecs/cs42l56.c b/sound/soc/codecs/cs42l56.c index 39f51fb..7cd5f76 100644 --- a/sound/soc/codecs/cs42l56.c +++ b/sound/soc/codecs/cs42l56.c @@ -115,52 +115,7 @@ static const struct reg_default cs42l56_reg_defaults[] = { static bool cs42l56_readable_register(struct device *dev, unsigned int reg) { switch (reg) { - case CS42L56_CHIP_ID_1: - case CS42L56_CHIP_ID_2: - case CS42L56_PWRCTL_1: - case CS42L56_PWRCTL_2: - case CS42L56_CLKCTL_1: - case CS42L56_CLKCTL_2: - case CS42L56_SERIAL_FMT: - case CS42L56_CLASSH_CTL: - case CS42L56_MISC_CTL: - case CS42L56_INT_STATUS: - case CS42L56_PLAYBACK_CTL: - case CS42L56_DSP_MUTE_CTL: - case CS42L56_ADCA_MIX_VOLUME: - case CS42L56_ADCB_MIX_VOLUME: - case CS42L56_PCMA_MIX_VOLUME: - case CS42L56_PCMB_MIX_VOLUME: - case CS42L56_ANAINPUT_ADV_VOLUME: - case CS42L56_DIGINPUT_ADV_VOLUME: - case CS42L56_MASTER_A_VOLUME: - case CS42L56_MASTER_B_VOLUME: - case CS42L56_BEEP_FREQ_ONTIME: - case CS42L56_BEEP_FREQ_OFFTIME: - case CS42L56_BEEP_TONE_CFG: - case CS42L56_TONE_CTL: - case CS42L56_CHAN_MIX_SWAP: - case CS42L56_AIN_REFCFG_ADC_MUX: - case CS42L56_HPF_CTL: - case CS42L56_MISC_ADC_CTL: - case CS42L56_GAIN_BIAS_CTL: - case CS42L56_PGAA_MUX_VOLUME: - case CS42L56_PGAB_MUX_VOLUME: - case CS42L56_ADCA_ATTENUATOR: - case CS42L56_ADCB_ATTENUATOR: - case CS42L56_ALC_EN_ATTACK_RATE: - case CS42L56_ALC_RELEASE_RATE: - case CS42L56_ALC_THRESHOLD: - case CS42L56_NOISE_GATE_CTL: - case CS42L56_ALC_LIM_SFT_ZC: - case CS42L56_AMUTE_HPLO_MUX: - case CS42L56_HPA_VOLUME: - case CS42L56_HPB_VOLUME: - case CS42L56_LOA_VOLUME: - case CS42L56_LOB_VOLUME: - case CS42L56_LIM_THRESHOLD_CTL: - case CS42L56_LIM_CTL_RELEASE_RATE: - case CS42L56_LIM_ATTACK_RATE: + case CS42L56_CHIP_ID_1 ... CS42L56_LIM_ATTACK_RATE: return true; default: return false;