From patchwork Thu Oct 8 16:12:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 7354061 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CC586BEEA4 for ; Thu, 8 Oct 2015 16:16:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DF492204A7 for ; Thu, 8 Oct 2015 16:16:07 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 955E12047B for ; Thu, 8 Oct 2015 16:16:06 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id C3BC62666F0; Thu, 8 Oct 2015 18:16:00 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, NO_DNS_FOR_FROM, RCVD_IN_DNSWL_LOW, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 79B27266811; Thu, 8 Oct 2015 18:13:37 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id B1B94266810; Thu, 8 Oct 2015 18:13:36 +0200 (CEST) Received: from mail-qg0-f52.google.com (mail-qg0-f52.google.com [209.85.192.52]) by alsa0.perex.cz (Postfix) with ESMTP id 268072666F0 for ; Thu, 8 Oct 2015 18:12:58 +0200 (CEST) Received: by qgez77 with SMTP id z77so46246941qge.1 for ; Thu, 08 Oct 2015 09:12:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=STbyCMzfQCxsj1dNHgNz6lu+l3aIWPg9vhzu2A9uV7U=; b=Az1fQL4gmNgJ7flYnVCSEC/N5gDrwzmsnECujWn8yZqSahjRxpxFLl7nPN8n1bGWm8 sNKCLa1fVTCvaAUL/V4yYFG6+OkCNSlR/22hAkajW+TSiErvbvY+NpHeku9lCUWb01Qu 2trtTHnUDQzMnJO1AWMiPRkcKHQyJ6f78sZkWiqu15uVzy6zOr/hNu4NR0P8TXENpZPc /xhaVgCWERJpW1YkHla+g4jiTHfzM+jvrPX4S5Gsh2Zkka6Vn8bdFgsH5HshbSagX5Sg f4r0g7m5103T1UOrhXNpuCdlTxUyKExYcykr0N7P3hbO1jNtsHteHzdkD5r+Ao6OUWZE 3Qtw== X-Received: by 10.140.96.99 with SMTP id j90mr9167315qge.92.1444320777517; Thu, 08 Oct 2015 09:12:57 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-49.washdc.fios.verizon.net. [74.96.105.49]) by smtp.gmail.com with ESMTPSA id s52sm18960467qge.19.2015.10.08.09.12.56 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Oct 2015 09:12:57 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: broonie@kernel.org, airlied@gmail.com, dri-devel@lists.freedesktop.org, alsa-devel@alsa-project.org, maruthi.bayyavarapu@amd.com, rajeevkumar.linux@gmail.com Date: Thu, 8 Oct 2015 12:12:38 -0400 Message-Id: <1444320760-21936-6-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1444320760-21936-1-git-send-email-alexander.deucher@amd.com> References: <1444320760-21936-1-git-send-email-alexander.deucher@amd.com> Cc: tiwai@suse.de, Maruthi Srinivas Bayyavarapu , lgirdwood@gmail.com Subject: [alsa-devel] [PATCH 5/8] ASoC : dwc : reconfigure dwc in 'resume' from 'suspend' X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Maruthi Srinivas Bayyavarapu dwc IP can be powered off during system suspend in some platforms (Ex: AMD CZ) as per design. After system is resumed, dwc needs to be programmed again to continue audio use case. Signed-off-by: Maruthi Bayyavarapu --- sound/soc/dwc/designware_i2s.c | 71 ++++++++++++++++++++++++++---------------- 1 file changed, 44 insertions(+), 27 deletions(-) diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c index a16b725..f7f38cb 100644 --- a/sound/soc/dwc/designware_i2s.c +++ b/sound/soc/dwc/designware_i2s.c @@ -98,6 +98,8 @@ struct dw_i2s_dev { unsigned int i2s_reg_comp1; unsigned int i2s_reg_comp2; struct device *dev; + u32 ccr; + u32 xfer_resolution; /* data related to DMA transfers b/w i2s and DMAC */ union dw_i2s_snd_dma_data play_dma_data; @@ -220,31 +222,58 @@ static int dw_i2s_startup(struct snd_pcm_substream *substream, return 0; } +static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) +{ + u32 ch_reg, irq; + struct i2s_clk_config_data *config = &dev->config; + + + i2s_disable_channels(dev, stream); + + for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + i2s_write_reg(dev->i2s_pbase, TCR(ch_reg), + dev->xfer_resolution); + i2s_write_reg(dev->i2s_pbase, TFCR(ch_reg), 0x02); + irq = i2s_read_reg(dev->i2s_pbase, IMR(ch_reg)); + i2s_write_reg(dev->i2s_pbase, IMR(ch_reg), irq & ~0x30); + i2s_write_reg(dev->i2s_pbase, TER(ch_reg), 1); + } else { + i2s_write_reg(dev->i2s_cbase, RCR(ch_reg), + dev->xfer_resolution); + i2s_write_reg(dev->i2s_cbase, RFCR(ch_reg), 0x07); + irq = i2s_read_reg(dev->i2s_cbase, IMR(ch_reg)); + i2s_write_reg(dev->i2s_cbase, IMR(ch_reg), irq & ~0x03); + i2s_write_reg(dev->i2s_cbase, RER(ch_reg), 1); + } + + } +} + static int dw_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); struct i2s_clk_config_data *config = &dev->config; - u32 ccr, xfer_resolution, ch_reg, irq; int ret; switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: config->data_width = 16; - ccr = 0x00; - xfer_resolution = 0x02; + dev->ccr = 0x00; + dev->xfer_resolution = 0x02; break; case SNDRV_PCM_FORMAT_S24_LE: config->data_width = 24; - ccr = 0x08; - xfer_resolution = 0x04; + dev->ccr = 0x08; + dev->xfer_resolution = 0x04; break; case SNDRV_PCM_FORMAT_S32_LE: config->data_width = 32; - ccr = 0x10; - xfer_resolution = 0x05; + dev->ccr = 0x10; + dev->xfer_resolution = 0x05; break; default: @@ -265,27 +294,9 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } - i2s_disable_channels(dev, substream->stream); - - for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - i2s_write_reg(dev->i2s_pbase, TCR(ch_reg), - xfer_resolution); - i2s_write_reg(dev->i2s_pbase, TFCR(ch_reg), 0x02); - irq = i2s_read_reg(dev->i2s_pbase, IMR(ch_reg)); - i2s_write_reg(dev->i2s_pbase, IMR(ch_reg), irq & ~0x30); - i2s_write_reg(dev->i2s_pbase, TER(ch_reg), 1); - } else { - i2s_write_reg(dev->i2s_cbase, RCR(ch_reg), - xfer_resolution); - i2s_write_reg(dev->i2s_cbase, RFCR(ch_reg), 0x07); - irq = i2s_read_reg(dev->i2s_cbase, IMR(ch_reg)); - i2s_write_reg(dev->i2s_cbase, IMR(ch_reg), irq & ~0x03); - i2s_write_reg(dev->i2s_cbase, RER(ch_reg), 1); - } - } + i2s_write_reg(dev->i2s_pbase, CCR, dev->ccr); - i2s_write_reg(dev->i2s_pbase, CCR, ccr); + dw_i2s_config(dev, substream->stream); config->sample_rate = params_rate(params); @@ -417,6 +428,12 @@ static int dw_i2s_resume(struct snd_soc_dai *dai) if (dev->capability & DW_I2S_MASTER) clk_enable(dev->clk); + + if (dai->playback_active) + dw_i2s_config(dev, SNDRV_PCM_STREAM_PLAYBACK); + if (dai->capture_active) + dw_i2s_config(dev, SNDRV_PCM_STREAM_CAPTURE); + return 0; }