From patchwork Fri Jan 8 23:22:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 7991141 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0D16EBEEE5 for ; Fri, 8 Jan 2016 23:23:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1D73F201DD for ; Fri, 8 Jan 2016 23:23:17 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id C2660201C7 for ; Fri, 8 Jan 2016 23:23:15 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 8297E265FF1; Sat, 9 Jan 2016 00:23:14 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, NO_DNS_FOR_FROM, RCVD_IN_DNSWL_NONE, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=no version=3.3.1 Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 4B5E5260544; Sat, 9 Jan 2016 00:22:30 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 3EB2C260544; Sat, 9 Jan 2016 00:22:28 +0100 (CET) Received: from mail-qg0-f68.google.com (mail-qg0-f68.google.com [209.85.192.68]) by alsa0.perex.cz (Postfix) with ESMTP id 053A62604EF for ; Sat, 9 Jan 2016 00:22:21 +0100 (CET) Received: by mail-qg0-f68.google.com with SMTP id 94so43227912qgt.1 for ; Fri, 08 Jan 2016 15:22:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=pPZr8PRaYFSoSIxdhWAMAq3vAyXRoCmlPkaD+ywFd58=; b=xZYKo3tnOegatTeyPtbkU0rQanolsCbf175FRsi9o0Ku/iA6vf4HBCGNrjKpycO9by 6EP+woXXHgneswUWfNcprNhfrBQ4UKJ8UM57kbTVa4nbJFYI3OX56QwlTATSCepXOtxj g7M1CegyZtJ8MZzB+ydaKez3ibhgxG9JnVs02pXHy+tT9nwiWRU6wWhsD4itRO1HgzsE 9iMhVio+VABlElggeMWcG5hvtshuAV/2MackmQf6PCt02YBP+0Gaojkw5MRi/u78zF1I wQoJETgCjx58xRrSl9JMCENQ/cK/1QN2AgM/bWStA49WeppxUffZUMkC/qk0T6jTGfSk Uohg== X-Received: by 10.140.109.100 with SMTP id k91mr19221838qgf.54.1452295340492; Fri, 08 Jan 2016 15:22:20 -0800 (PST) Received: from cm.localdomain (static-74-96-105-49.washdc.fios.verizon.net. [74.96.105.49]) by smtp.gmail.com with ESMTPSA id f83sm43834730qkb.25.2016.01.08.15.22.19 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 08 Jan 2016 15:22:20 -0800 (PST) From: Alex Deucher X-Google-Original-From: Alex Deucher To: airlied@gmail.com, dri-devel@lists.freedesktop.org, broonie@kernel.org, alsa-devel@alsa-project.org, maruthi.bayyavarapu@amd.com, rajeevkumar.linux@gmail.com Date: Fri, 8 Jan 2016 18:22:03 -0500 Message-Id: <1452295331-28476-2-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1452295331-28476-1-git-send-email-alexander.deucher@amd.com> References: <1452295331-28476-1-git-send-email-alexander.deucher@amd.com> MIME-Version: 1.0 Cc: tiwai@suse.de, Alex Deucher , lgirdwood@gmail.com Subject: [alsa-devel] [PATCH 1/9] drm/amdgpu/cgs: add an interface to access PCI resources X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP This provides an interface to get access to the base address of PCI resources (MMIO, DOORBELL, etc.). Only MMIO and DOORBELL are implemented right now. This is necessary to properly utilize shared drivers on platform devices. IP modules can use this interface to get the base address of the resource and add any additional offset and set the size when setting up the platform driver(s). Acked-by: Dave Airlie Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 36 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/include/cgs_common.h | 34 ++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index 59485d0..a081dda 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -398,6 +398,41 @@ static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr, WARN(ret, "pci_write_config_dword error"); } + +static int amdgpu_cgs_get_pci_resource(void *cgs_device, + enum cgs_resource_type resource_type, + uint64_t size, + uint64_t offset, + uint64_t *resource_base) +{ + CGS_FUNC_ADEV; + + if (resource_base == NULL) + return -EINVAL; + + switch (resource_type) { + case CGS_RESOURCE_TYPE_MMIO: + if (adev->rmmio_size == 0) + return -ENOENT; + if ((offset + size) > adev->rmmio_size) + return -EINVAL; + *resource_base = adev->rmmio_base; + return 0; + case CGS_RESOURCE_TYPE_DOORBELL: + if (adev->doorbell.size == 0) + return -ENOENT; + if ((offset + size) > adev->doorbell.size) + return -EINVAL; + *resource_base = adev->doorbell.base; + return 0; + case CGS_RESOURCE_TYPE_FB: + case CGS_RESOURCE_TYPE_IO: + case CGS_RESOURCE_TYPE_ROM: + default: + return -EINVAL; + } +} + static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device, unsigned table, uint16_t *size, uint8_t *frev, uint8_t *crev) @@ -1041,6 +1076,7 @@ static const struct cgs_ops amdgpu_cgs_ops = { amdgpu_cgs_write_pci_config_byte, amdgpu_cgs_write_pci_config_word, amdgpu_cgs_write_pci_config_dword, + amdgpu_cgs_get_pci_resource, amdgpu_cgs_atom_get_data_table, amdgpu_cgs_atom_get_cmd_table_revs, amdgpu_cgs_atom_exec_cmd_table, diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h index 03affb3..713aec9 100644 --- a/drivers/gpu/drm/amd/include/cgs_common.h +++ b/drivers/gpu/drm/amd/include/cgs_common.h @@ -122,6 +122,17 @@ struct cgs_system_info { uint64_t padding[13]; }; +/* + * enum cgs_resource_type - GPU resource type + */ +enum cgs_resource_type { + CGS_RESOURCE_TYPE_MMIO = 0, + CGS_RESOURCE_TYPE_FB, + CGS_RESOURCE_TYPE_IO, + CGS_RESOURCE_TYPE_DOORBELL, + CGS_RESOURCE_TYPE_ROM, +}; + /** * struct cgs_clock_limits - Clock limits * @@ -417,6 +428,23 @@ typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr, typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr, uint32_t value); + +/** + * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) + * @cgs_device: opaque device handle + * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) + * @size: size of the region + * @offset: offset from the start of the region + * @resource_base: base address (not including offset) returned + * + * Return: 0 on success, -errno otherwise + */ +typedef int (*cgs_get_pci_resource_t)(void *cgs_device, + enum cgs_resource_type resource_type, + uint64_t size, + uint64_t offset, + uint64_t *resource_base); + /** * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table * @cgs_device: opaque device handle @@ -593,6 +621,8 @@ struct cgs_ops { cgs_write_pci_config_byte_t write_pci_config_byte; cgs_write_pci_config_word_t write_pci_config_word; cgs_write_pci_config_dword_t write_pci_config_dword; + /* PCI resources */ + cgs_get_pci_resource_t get_pci_resource; /* ATOM BIOS */ cgs_atom_get_data_table_t atom_get_data_table; cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; @@ -708,5 +738,9 @@ struct cgs_device CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) #define cgs_query_system_info(dev, sys_info) \ CGS_CALL(query_system_info, dev, sys_info) +#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ + resource_base) \ + CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ + resource_base) #endif /* _CGS_COMMON_H */