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[90.41.34.247]) by smtp.gmail.com with ESMTPSA id g3sm24306496wjw.31.2016.01.18.07.26.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jan 2016 07:26:46 -0800 (PST) From: Arnaud Mouiche To: Timur Tabi , Nicolin Chen , Xiubo Li , Liam Girdwood , Mark Brown , alsa-devel@alsa-project.org, Caleb Crome Date: Mon, 18 Jan 2016 16:26:09 +0100 Message-Id: <1453130771-24419-5-git-send-email-arnaud.mouiche@invoxia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1453130771-24419-1-git-send-email-arnaud.mouiche@invoxia.com> References: <1453130771-24419-1-git-send-email-arnaud.mouiche@invoxia.com> Cc: Arnaud Mouiche Subject: [alsa-devel] [PATCH v3 4/6] ASoC: fsl_ssi: Fix samples being dropped as Playback startup X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP If the capture is already running while playback is started, it is highly probable (>80% in a 8 channels scenario) that samples are lost between the DMA and TX fifo. The reason is that SIER.TDMAE is set before STCR.TFEN0, leaving a time window where the FIFO doesn't receive the samples written by the DMA. This particular case happened only if capture is already enabled as SCR.SSIEN is already set at the playback startup instant. Signed-off-by: Arnaud Mouiche Tested-By: Caleb Crome --- sound/soc/fsl/fsl_ssi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 13613fd..c9ba8ca 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -488,9 +488,9 @@ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, * (online configuration) */ if (enable) { - regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier); regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr); regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr); + regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier); } else { u32 sier; u32 srcr;