From patchwork Mon Feb 15 14:11:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 8315691 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1618B9F372 for ; Mon, 15 Feb 2016 14:13:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3EA69203B8 for ; Mon, 15 Feb 2016 14:13:08 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 0A47E2039E for ; Mon, 15 Feb 2016 14:13:07 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 275B426548E; Mon, 15 Feb 2016 15:13:04 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 3BB8B2651D3; Mon, 15 Feb 2016 15:11:55 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 5ED452651A9; Mon, 15 Feb 2016 15:11:54 +0100 (CET) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by alsa0.perex.cz (Postfix) with ESMTP id E8316261ADB for ; Mon, 15 Feb 2016 15:11:46 +0100 (CET) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id u1FEBkAa006685; Mon, 15 Feb 2016 08:11:46 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1FEBkMK018816; Mon, 15 Feb 2016 08:11:46 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Mon, 15 Feb 2016 08:11:45 -0600 Received: from dflp33.itg.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1FEBcmY032690; Mon, 15 Feb 2016 08:11:44 -0600 From: Peter Ujfalusi To: Mark Brown , Liam Girdwood Date: Mon, 15 Feb 2016 16:11:33 +0200 Message-ID: <1455545495-20292-3-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.7.1 In-Reply-To: <1455545495-20292-1-git-send-email-peter.ujfalusi@ti.com> References: <1455545495-20292-1-git-send-email-peter.ujfalusi@ti.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, Jyri Sarha Subject: [alsa-devel] [PATCH 2/4] ASoC: davinci-mcasp: Improve the sysclk selection X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP When McASP is master the bclk can be generated from two main source: AUXCLK: functional clock for McASP or AHCLK: from external source or internal mux in dra7x family With this patch it is possible to select between the two source. The patch is not breaking existing machine drivers since historically the clk_id was ignored and left as 0 in all cases. When output clock is configured - which can be only the AHCLK, we select the AUXCLK as source for the internal HCLK. In this case the HCLK rate is the same as the output clock. Signed-off-by: Peter Ujfalusi --- include/dt-bindings/sound/ti-mcasp.h | 4 ++++ sound/soc/davinci/davinci-mcasp.c | 34 +++++++++++++++++++++++++++------- 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/include/dt-bindings/sound/ti-mcasp.h b/include/dt-bindings/sound/ti-mcasp.h index 03519ab67b44..86ee4d0d79b5 100644 --- a/include/dt-bindings/sound/ti-mcasp.h +++ b/include/dt-bindings/sound/ti-mcasp.h @@ -1,6 +1,10 @@ #ifndef _DT_BINDINGS_TI_MCASP_H #define _DT_BINDINGS_TI_MCASP_H +/* Source of High-frequency transmit/receive clock */ +#define MCASP_CLK_HCLK_AHCLK 0 /* AHCLKX/R */ +#define MCASP_CLK_HCLK_AUXCLK 1 /* Internal functional clock */ + /* clock divider IDs */ #define MCASP_CLKDIV_AUXCLK 0 /* HCLK divider from AUXCLK */ #define MCASP_CLKDIV_BCLK 1 /* BCLK divider from HCLK */ diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c index a4e40606742a..1bd86c8e7bc8 100644 --- a/sound/soc/davinci/davinci-mcasp.c +++ b/sound/soc/davinci/davinci-mcasp.c @@ -596,18 +596,38 @@ static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); pm_runtime_get_sync(mcasp->dev); - if (dir == SND_SOC_CLOCK_OUT) { + + if (dir == SND_SOC_CLOCK_IN) { + switch (clk_id) { + case MCASP_CLK_HCLK_AHCLK: + mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, + AHCLKXE); + mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, + AHCLKRE); + mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); + break; + case MCASP_CLK_HCLK_AUXCLK: + mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, + AHCLKXE); + mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, + AHCLKRE); + break; + default: + dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id); + goto out; + } + } else { + /* Select AUXCLK as HCLK */ mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); - } else { - mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); - mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); - mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); } - + /* + * When AHCLK X/R is selected to be output it means that the HCLK is + * the same clock - coming via AUXCLK. + */ mcasp->sysclk_freq = freq; - +out: pm_runtime_put(mcasp->dev); return 0; }