From patchwork Thu May 5 08:03:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 9021551 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 097FBBF29F for ; Thu, 5 May 2016 08:05:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2066E20416 for ; Thu, 5 May 2016 08:05:10 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id E9CE2203FB for ; Thu, 5 May 2016 08:05:08 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 93B63265DE4; Thu, 5 May 2016 10:05:07 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 8895F265D05; Thu, 5 May 2016 10:04:00 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id CC16C265E22; Thu, 5 May 2016 10:03:59 +0200 (CEST) Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by alsa0.perex.cz (Postfix) with ESMTP id 4635C265A3E for ; Thu, 5 May 2016 10:03:50 +0200 (CEST) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id BBC4D266740 From: Enric Balletbo i Serra To: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, alsa-devel@alsa-project.org Date: Thu, 5 May 2016 10:03:36 +0200 Message-Id: <1462435421-21205-3-git-send-email-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1462435421-21205-1-git-send-email-enric.balletbo@collabora.com> References: <1462435421-21205-1-git-send-email-enric.balletbo@collabora.com> Cc: Mark Brown , John Keeping , Heiko Stuebner Subject: [alsa-devel] [PATCH 2/7] ASoC: rockchip: Revert "ASoC: rockchip: i2s: separate capture and playback" X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: John Keeping This reverts commit eba65d179c1149cf79e68608d452631f33d7f017. This broke audio on Veyron Jerry Chromebooks and I now cannot reproduce the problem I was trying to fix even with this commit reverted, so it seems that this was completely the wrong thing to do. Reported-by: Enric Balletbo Serra Signed-off-by: John Keeping --- sound/soc/rockchip/rockchip_i2s.c | 72 ++++++++++++++++++++++----------------- 1 file changed, 40 insertions(+), 32 deletions(-) diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 34743ec..574c6af 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -82,8 +82,8 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_TXS_START, - I2S_XFER_TXS_START); + I2S_XFER_TXS_START | I2S_XFER_RXS_START, + I2S_XFER_TXS_START | I2S_XFER_RXS_START); i2s->tx_start = true; } else { @@ -92,23 +92,27 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); - regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_TXS_START, - I2S_XFER_TXS_STOP); - - regmap_update_bits(i2s->regmap, I2S_CLR, - I2S_CLR_TXC, - I2S_CLR_TXC); + if (!i2s->rx_start) { + regmap_update_bits(i2s->regmap, I2S_XFER, + I2S_XFER_TXS_START | + I2S_XFER_RXS_START, + I2S_XFER_TXS_STOP | + I2S_XFER_RXS_STOP); - regmap_read(i2s->regmap, I2S_CLR, &val); + regmap_update_bits(i2s->regmap, I2S_CLR, + I2S_CLR_TXC | I2S_CLR_RXC, + I2S_CLR_TXC | I2S_CLR_RXC); - /* Should wait for clear operation to finish */ - while (val & I2S_CLR_TXC) { regmap_read(i2s->regmap, I2S_CLR, &val); - retry--; - if (!retry) { - dev_warn(i2s->dev, "fail to clear\n"); - break; + + /* Should wait for clear operation to finish */ + while (val) { + regmap_read(i2s->regmap, I2S_CLR, &val); + retry--; + if (!retry) { + dev_warn(i2s->dev, "fail to clear\n"); + break; + } } } } @@ -124,8 +128,8 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_RXS_START, - I2S_XFER_RXS_START); + I2S_XFER_TXS_START | I2S_XFER_RXS_START, + I2S_XFER_TXS_START | I2S_XFER_RXS_START); i2s->rx_start = true; } else { @@ -134,23 +138,27 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); - regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_RXS_START, - I2S_XFER_RXS_STOP); - - regmap_update_bits(i2s->regmap, I2S_CLR, - I2S_CLR_RXC, - I2S_CLR_RXC); + if (!i2s->tx_start) { + regmap_update_bits(i2s->regmap, I2S_XFER, + I2S_XFER_TXS_START | + I2S_XFER_RXS_START, + I2S_XFER_TXS_STOP | + I2S_XFER_RXS_STOP); - regmap_read(i2s->regmap, I2S_CLR, &val); + regmap_update_bits(i2s->regmap, I2S_CLR, + I2S_CLR_TXC | I2S_CLR_RXC, + I2S_CLR_TXC | I2S_CLR_RXC); - /* Should wait for clear operation to finish */ - while (val & I2S_CLR_RXC) { regmap_read(i2s->regmap, I2S_CLR, &val); - retry--; - if (!retry) { - dev_warn(i2s->dev, "fail to clear\n"); - break; + + /* Should wait for clear operation to finish */ + while (val) { + regmap_read(i2s->regmap, I2S_CLR, &val); + retry--; + if (!retry) { + dev_warn(i2s->dev, "fail to clear\n"); + break; + } } } }