From patchwork Fri Jun 3 20:09:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Handrigan X-Patchwork-Id: 9153971 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DDBC960751 for ; Fri, 3 Jun 2016 20:09:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CFACB25404 for ; Fri, 3 Jun 2016 20:09:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C483F28335; Fri, 3 Jun 2016 20:09:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D1CD225404 for ; Fri, 3 Jun 2016 20:09:58 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id DF8A9266DA8; Fri, 3 Jun 2016 22:09:56 +0200 (CEST) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 15D77266D4E; Fri, 3 Jun 2016 22:09:18 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 5EE53266CD7; Fri, 3 Jun 2016 22:09:17 +0200 (CEST) Received: from mx0a-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) by alsa0.perex.cz (Postfix) with ESMTP id B4205266812 for ; Fri, 3 Jun 2016 22:09:09 +0200 (CEST) Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u53K96o7009718; Fri, 3 Jun 2016 15:09:06 -0500 Authentication-Results: ppops.net; spf=pass smtp.mailfrom=Paul.Handrigan@cirrus.com Received: from mail1.cirrus.com (mail1.cirrus.com [141.131.3.20]) by mx0a-001ae601.pphosted.com with ESMTP id 2378r0e03h-1; Fri, 03 Jun 2016 15:09:06 -0500 Received: from ex3.ad.cirrus.com (ex3.ad.cirrus.com [141.131.36.34]) by mail1.cirrus.com (Postfix) with ESMTP id 7063034053; Fri, 3 Jun 2016 15:10:50 -0500 (CDT) Received: from localhost (141.131.38.212) by InternalRelay (141.131.36.34) with Microsoft SMTP Server id 14.3.248.2; Fri, 3 Jun 2016 15:09:06 -0500 From: To: Date: Fri, 3 Jun 2016 15:09:06 -0500 Message-ID: <1464984546-2672-2-git-send-email-Paul.Handrigan@cirrus.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464984546-2672-1-git-send-email-Paul.Handrigan@cirrus.com> References: <1464984546-2672-1-git-send-email-Paul.Handrigan@cirrus.com> MIME-Version: 1.0 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf-001ae601.pphosted.com ip4:141.131.128.20 ip4:141.131.3.20 ip4:213.128.236.230 ip4:87.246.98.25 ip4:87.246.78.26 -all X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1606030223 Cc: Paul Handrigan , brian.austin@cirrus.com, broonie@kernel.org, lgirdwood@gmail.com, robh+dt@kernel.org Subject: [alsa-devel] [PATCH v6 2/2] ASoC: cs35l33: Add device tree bindings file for cs35l33 X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paul Handrigan Add device tree bindings file for the cs35l33 8V boosted class D amplifier. Signed-off-by: Paul Handrigan --- .../devicetree/bindings/sound/cs35l33.txt | 114 +++++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cs35l33.txt diff --git a/Documentation/devicetree/bindings/sound/cs35l33.txt b/Documentation/devicetree/bindings/sound/cs35l33.txt new file mode 100644 index 0000000..01fa8fd --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs35l33.txt @@ -0,0 +1,114 @@ +CS35L33 Speaker Amplifier + +Required properties: + + - compatible : "cirrus,cs35l33" + + - reg : the I2C address of the device for I2C + + - VA-supply, VP-supply : power supplies for the device, + as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + +Optional properties: + + - reset-gpios : gpio used to reset the amplifier + + - interrupt-parent : Specifies the phandle of the interrupt controller to + which the IRQs from CS35L33 are delivered to. + - interrupts : IRQ line info CS35L33. + (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + for further information relating to interrupt properties) + + - boost-ctl : Booster voltage use to supply the amp. If the value is + 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with + a value of 1 and will increase at a step size of 100mV until a maximum of + 8000mV. + + - ramp-rate : On power up, it affects the time from when the power + up sequence begins to the time the audio reaches a full-scale output. + On power down, it affects the time from when the power-down sequence + begins to when the amplifier disables the PWM outputs. If this property + is not set then soft ramping will be disabled and ramp time would be + 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms, + 60ms,100ms,175ms respectively for 48KHz sample rate. + + - boost-ipk : The maximum current allowed for the boost converter. + The range starts at 1850mA (0xF0) and goes to a maximum of 3600mA (0xE0) + with a step size of 15.625mA. The default is 2500mA (0x90). + + - hg-algo : Parameters for internal Class H/G algorithm that + controls the amplifier supplies. + + - mem-depth : Memory depth for the Class H/G algorithm measured in LRCLK + cycles. If this property is set to 0, 1, 2, or 3 then the memory depths + will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles. + + release-rate : The number of consecutive LRCLK periods before allowing + release condition tracking updates. The number of LRCLK periods start + at 3 to a maximum of 255. + + - ldo-thld : Configures the signal threshold at which the PWM output stage + enters LDO operation. Starts as a default value of 50mV for a value of 1 + and increases with a step size of 50mV to a maximum of 750mV (value of + 0xF). + + - ldo-path-disable : This is a boolean property. If present, the H/G + algorithm uses the max detection path. If not present, the LDO + detection path is used. + + - ldo-entry-delay : The LDO entry delay in milliseconds before the H/G + algorithm switches to the LDO voltage. This property can be set to values + from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms. + The default is 100ms. + + - vp-hg-auto : This is a boolean property. When set, class H/G VPhg + automatic updating is enabled. + + - vp-hg : Class H/G algorithm VPhg. Controls the H/G algorithm's + reference to the VP voltage for when to start generating a boosted VBST. + The reference voltage starts at 3000mV with a value of 0x3 and is increased + by 100mV per step to a maximum of 5500mV. + + - vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is + allowed to increase to a higher voltage when using VPhg automatic + tracking. This property can be set to values from 0 to 3 with rates of 128 + periods, 2048 periods, 32768 periods, and 524288 periods. + The default is 32768 periods. + + - vp-hg-va : VA calculation reference for automatic VPhg tracking using VPMON. + This property can be set to values from 0 to 6 starting at 1800mV with a + step size of 50mV up to a maximum value of 1750mV. Default is 1800mV. + + +Example: + +cs35l33: cs35l33@40 { + compatible = "cirrus,cs35l33"; + reg = <0x40>; + + VA-supply = <&ldo5_reg>; + VP-supply = <&ldo5_reg>; + + interrupt-parent = <&gpio8>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&cs47l91 34 0>; + + ramp-rate = <0x0>; + boost-ctl = <0x30>; /* VBST = 8000mV */ + boost-ipk = <0xE0>; /* 3600mA */ + + hg-algo { + mem-depth = <0x3>; + release-rate = <0x3>; + hd-rm = <0xA>; + ldo-thld = <0x1>; + ldo-path-disable = <0x0>; + ldo-entry-delay=<0x4>; + vp-hg-auto; + vp-hg=<0xF>; + vp-hg-rate=<0x2>; + vp-hg-va=<0x0>; + }; +};