From patchwork Mon Dec 18 02:52:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 10118199 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E0DDC60327 for ; Mon, 18 Dec 2017 02:56:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C90332907D for ; Mon, 18 Dec 2017 02:56:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BDFCF290A0; Mon, 18 Dec 2017 02:56:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=no version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC5FE2907D for ; Mon, 18 Dec 2017 02:56:41 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 4BA762674D5; Mon, 18 Dec 2017 03:53:52 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id AB2282671EC; Mon, 18 Dec 2017 03:53:43 +0100 (CET) Received: from mail-pl0-f68.google.com (mail-pl0-f68.google.com [209.85.160.68]) by alsa0.perex.cz (Postfix) with ESMTP id 96D3E2671A3 for ; Mon, 18 Dec 2017 03:53:35 +0100 (CET) Received: by mail-pl0-f68.google.com with SMTP id bi12so3997581plb.6 for ; Sun, 17 Dec 2017 18:53:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lDmj3tE3Dw7qSV4Tg5G7uoNBJCV3xlOFjICgcAXYFPQ=; b=u15u3DN9tp8UKFHv5/ed9EZJnr5jyHG/ojTfJx1dDcSJUdrvh4GPw0i/mWJDQIhbAw J2/d4C66nxAH7TcYKYovADGss81iJipGcfBkHOlFRwbYGDMO6aY115YMGZ/UFV5X04kM xWrNEOITst7WAsXhz+GuF39JrrdmDftgDDTL8opBk36UpsVDLnfjeqzAI3eSdRO5o/pT u9vUIUcC+ciHlI2TN1JZZxhd1HGesaY7k+C29+q3I7nqpTNSEziRLpep1+Xgd8gjrUGw B6dM/xMDgiPtZxNiuxN/eAvSVW9oNcq0vSzY4vHPKNBCNcH8u/mLvf7u5jyGSTZ59OZg X4jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lDmj3tE3Dw7qSV4Tg5G7uoNBJCV3xlOFjICgcAXYFPQ=; b=aOqf9QTo3QWeWoVWfgVZvXJTJES++AzYUMSjfpMOgDoI8wCI9nm2R5xbOhwsP8ggve /3s0eKZ0aETG66torxPzdmmSgyQK1j5xdLUrINnWZupyaS3pcBryd+Bp262/9s9rOlQr 9tnl5SxoGT6Zgp7AqEuOIu+vNTsUdvRLcj/K5uxMYFby2N6I2neDrTq/mBjDMUQCNSUo oLE9c6scRX8mHGmdWGWJtWSCh1F1SZFGe7pFNNllHW/i3haip5GmXH0xISxT7QTXciUl mnyrUuFS7ogwp5Y44n8+os3XWJklgvZYcm0fUw1w4K3plGU3ayh4QqLCCu+FVGtLJOiK kvQw== X-Gm-Message-State: AKGB3mInQ+PP8CVdhK4sboiVN4s9WDGmFdwbiAv1ajJwK1vJ/O6N14ty l4npt7brDMGIcKMpAjs6dLY= X-Google-Smtp-Source: ACJfBovXxzo8elUnr24/GRC397iqlgGLZAw80qAiCV1cwOT26HoQizmJWFt8ew923s2Ge13az4Ccow== X-Received: by 10.84.244.12 with SMTP id g12mr20491936pll.69.1513565614524; Sun, 17 Dec 2017 18:53:34 -0800 (PST) Received: from Asurada-CZ80.localdomain (c-73-231-2-134.hsd1.ca.comcast.net. [73.231.2.134]) by smtp.gmail.com with ESMTPSA id x6sm21943630pfx.29.2017.12.17.18.53.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Dec 2017 18:53:34 -0800 (PST) From: Nicolin Chen To: timur@tabi.org, broonie@kernel.org Date: Sun, 17 Dec 2017 18:52:10 -0800 Message-Id: <1513565530-33957-12-git-send-email-nicoleotsuka@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513565530-33957-1-git-send-email-nicoleotsuka@gmail.com> References: <1513565530-33957-1-git-send-email-nicoleotsuka@gmail.com> Cc: mail@maciej.szmigiero.name, kernel@pengutronix.de, lgirdwood@gmail.com, alsa-devel@alsa-project.org, caleb@crome.org, linux-kernel@vger.kernel.org, arnaud.mouiche@invoxia.com, lukma@denx.de, fabio.estevam@nxp.com, linuxppc-dev@lists.ozlabs.org Subject: [alsa-devel] [PATCH v4 11/11] ASoC: fsl_ssi: Define ternary macros to simplify code X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Some regmap code looks redudant. So simplify it. Signed-off-by: Nicolin Chen Tested-by: Maciej S. Szmigiero Reviewed-by: Maciej S. Szmigiero --- sound/soc/fsl/fsl_ssi.c | 27 +++++++++++---------------- sound/soc/fsl/fsl_ssi.h | 4 ++++ 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 2b3915c..aecd00f 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -408,13 +408,10 @@ static void fsl_ssi_rxtx_config(struct fsl_ssi *ssi, bool enable) */ static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx) { - if (is_rx) { - regmap_update_bits(ssi->regs, REG_SSI_SOR, - SSI_SOR_RX_CLR, SSI_SOR_RX_CLR); - } else { - regmap_update_bits(ssi->regs, REG_SSI_SOR, - SSI_SOR_TX_CLR, SSI_SOR_TX_CLR); - } + bool tx = !is_rx; + + regmap_update_bits(ssi->regs, REG_SSI_SOR, + SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); } /** @@ -681,6 +678,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, struct snd_soc_dai *dai, struct snd_pcm_hw_params *hw_params) { + bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); struct regmap *regs = ssi->regs; int synchronous = ssi->cpu_dai_drv.symmetric_rates, ret; @@ -768,10 +766,9 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, (psr ? SSI_SxCCR_PSR : 0); mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) - regmap_update_bits(regs, REG_SSI_STCCR, mask, stccr); - else - regmap_update_bits(regs, REG_SSI_SRCCR, mask, stccr); + /* STCCR is used for RX in synchronous mode */ + tx2 = tx || synchronous; + regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr); if (!baudclk_is_used) { ret = clk_set_rate(ssi->baudclk, baudrate); @@ -799,6 +796,7 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *dai) { + bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); struct regmap *regs = ssi->regs; unsigned int channels = params_channels(hw_params); @@ -849,11 +847,8 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, } /* In synchronous mode, the SSI uses STCCR for capture */ - if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || - ssi->cpu_dai_drv.symmetric_rates) - regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_WL_MASK, wl); - else - regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_WL_MASK, wl); + tx2 = tx || ssi->cpu_dai_drv.symmetric_rates; + regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl); return 0; } diff --git a/sound/soc/fsl/fsl_ssi.h b/sound/soc/fsl/fsl_ssi.h index b610087..de2fdc5 100644 --- a/sound/soc/fsl/fsl_ssi.h +++ b/sound/soc/fsl/fsl_ssi.h @@ -35,10 +35,12 @@ #define REG_SSI_STCR 0x1c /* SSI Receive Configuration Register */ #define REG_SSI_SRCR 0x20 +#define REG_SSI_SxCR(tx) ((tx) ? REG_SSI_STCR : REG_SSI_SRCR) /* SSI Transmit Clock Control Register */ #define REG_SSI_STCCR 0x24 /* SSI Receive Clock Control Register */ #define REG_SSI_SRCCR 0x28 +#define REG_SSI_SxCCR(tx) ((tx) ? REG_SSI_STCCR : REG_SSI_SRCCR) /* SSI FIFO Control/Status Register */ #define REG_SSI_SFCSR 0x2c /* @@ -67,6 +69,7 @@ #define REG_SSI_STMSK 0x48 /* SSI Receive Time Slot Mask Register */ #define REG_SSI_SRMSK 0x4c +#define REG_SSI_SxMSK(tx) ((tx) ? REG_SSI_STMSK : REG_SSI_SRMSK) /* * SSI AC97 Channel Status Register * @@ -249,6 +252,7 @@ #define SSI_SOR_CLKOFF 0x00000040 #define SSI_SOR_RX_CLR 0x00000020 #define SSI_SOR_TX_CLR 0x00000010 +#define SSI_SOR_xX_CLR(tx) ((tx) ? SSI_SOR_TX_CLR : SSI_SOR_RX_CLR) #define SSI_SOR_INIT 0x00000008 #define SSI_SOR_WAIT_SHIFT 1 #define SSI_SOR_WAIT_MASK 0x00000006