From patchwork Thu Dec 28 20:09:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 10135829 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7A35C60388 for ; Thu, 28 Dec 2017 20:11:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6C2DF2CE00 for ; Thu, 28 Dec 2017 20:11:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 600A12D8EA; Thu, 28 Dec 2017 20:11:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,T_DKIM_INVALID autolearn=no version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7F7302CE00 for ; Thu, 28 Dec 2017 20:11:46 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 8D069267214; Thu, 28 Dec 2017 21:10:41 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 9E521267214; Thu, 28 Dec 2017 21:10:40 +0100 (CET) Received: from mail-pl0-f67.google.com (mail-pl0-f67.google.com [209.85.160.67]) by alsa0.perex.cz (Postfix) with ESMTP id 90B3A2671E9 for ; Thu, 28 Dec 2017 21:10:36 +0100 (CET) Received: by mail-pl0-f67.google.com with SMTP id bd8so21686238plb.9 for ; Thu, 28 Dec 2017 12:10:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gateworks-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0hRmpk9tJ6ATgoATvAYnb5ZPpGJNoJD9aTyROa1Zce4=; b=qipA0YaX3P8J5i22/Hak5syNDAJ7WQyTS49YeDaOmhgLPrEC1/unWaE6GW4IHyCvC4 JEePEFILlayUR+rgsNVacEvJ8tMA7ssDUDqGc+ikGP6y3PIDtC7DU27n/BzBUnchu2PP YtexmlFEmf9Oorxp1CwPLvq2TDQa6mVVCsze6NrHIc5dNcRdrReMO3xorkZ0Tl2IG+6Q HufN6n+FP2sGhgfXvzBqZpMgf1unwTk/VCrZEPba/tGPHEnPlg8/C+/rIoMek8iEOtu7 hsQZeVXa3FaR41prCY5L3mvCMptZnZNp1bnE60lbCfWdjcOJJ/JZw+RnlywRTf5CwZf5 SD/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0hRmpk9tJ6ATgoATvAYnb5ZPpGJNoJD9aTyROa1Zce4=; b=ZRnuAp8E1UjUANvhwbWtXYObd3/xTsx4BqtAGPvV9geR7y0oB0oqm+EXTiwJqJnaK7 Rcz+uY0vQhw0jcXKyYnfZTCCUM2e72SjdaUAmI/OQC4a1GGjAf9kxfDOJIM70WM+nqpD sNF0g4HwcQ7qz0OeAJfB63duRIzGTw9D0oCqn8GHXnqcNGUE8c/3P+Pugm4Y6VtYZV9l /BnxsOsFr/Waf977MHNUYtWT3uNTV3Iuy2gonb3AiDzhfqo2V+qtIvUAwnxi21am0HFh 1Qr/TK0sERud7N81jy6KWCBgBechvDXQTgcafEYNhglAx8nPPtzqHmlEw7i6FEP0J159 ch3w== X-Gm-Message-State: AKGB3mLVdYsHS43o2LUoVLp7VNKdwp4KYncny6meXc7Ol/t54txZAT1T Qd1RKGtZ3ArqYlvQnVX+jC946Q== X-Google-Smtp-Source: ACJfBouabI6cAwUPTeVHlnGuzN/oVy7fB4LccJ9efVQKvyZeyXm3saf6aJuTbuR/FkuxR9XBDlis4g== X-Received: by 10.84.229.5 with SMTP id b5mr33372765plk.405.1514491833160; Thu, 28 Dec 2017 12:10:33 -0800 (PST) Received: from tharvey.pdc.gateworks.com (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by smtp.gmail.com with ESMTPSA id 6sm49241510pgf.54.2017.12.28.12.10.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Dec 2017 12:10:31 -0800 (PST) From: Tim Harvey To: linux-media@vger.kernel.org, alsa-devel@alsa-project.org Date: Thu, 28 Dec 2017 12:09:49 -0800 Message-Id: <1514491789-8697-7-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514491789-8697-1-git-send-email-tharvey@gateworks.com> References: <1514491789-8697-1-git-send-email-tharvey@gateworks.com> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Verkuil , Mauro Carvalho Chehab , Philipp Zabel , Steve Longerbeam , shawnguo@kernel.org Subject: [alsa-devel] [PATCH v6 6/6] ARM: dts: imx: Add TDA19971 HDMI Receiver to GW551x X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Cc: Shawn Guo Signed-off-by: Tim Harvey --- v6: no changes v5: - add missing audmux config --- arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 138 ++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 30d4662..749548a 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -46,6 +46,8 @@ */ #include +#include +#include / { /* these are used by bootloader for disabling nodes */ @@ -98,6 +100,50 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + sound-digital { + compatible = "simple-audio-card"; + simple-audio-card,name = "tda1997x-audio"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + + cpu { + sound-dai = <&ssi2>; + }; + + codec { + bitclock-master; + frame-master; + sound-dai = <&tda1997x>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ + status = "okay"; + + ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; + }; }; &can1 { @@ -263,6 +309,60 @@ #gpio-cells = <2>; }; + tda1997x: tda1997x@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3>; + AVDD-supply = <®_1p8b>; + DVDD-supply = <®_1p8a>; + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same cycle + * which we map to VP[15:08]<->CSI_DATA[19:12] + */ + nxp,vidout-portcfg = + /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <16>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; + bus-width = <16>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; }; &pcie { @@ -320,6 +420,14 @@ }; &iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 @@ -375,6 +483,30 @@ >; }; + pinctrl_ipu1_csi0: ipu1_csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ @@ -399,6 +531,12 @@ >; }; + pinctrl_tda1997x: tda1997xgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1