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Mon, 12 Mar 2018 01:32:35 -0500 From: Vijendar Mukunda To: , , Date: Mon, 12 Mar 2018 12:04:15 +0530 Message-ID: <1520836460-21809-3-git-send-email-Vijendar.Mukunda@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520836460-21809-1-git-send-email-Vijendar.Mukunda@amd.com> References: <1520836460-21809-1-git-send-email-Vijendar.Mukunda@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(39380400002)(39860400002)(376002)(396003)(346002)(2980300002)(428003)(199004)(189003)(105586002)(106466001)(8936002)(68736007)(53416004)(8676002)(2906002)(5660300001)(97736004)(81156014)(81166006)(76176011)(305945005)(356003)(51416003)(7696005)(316002)(50466002)(48376002)(36756003)(54906003)(478600001)(72206003)(110136005)(16586007)(2950100002)(6666003)(336012)(47776003)(39060400002)(50226002)(4326008)(53936002)(77096007)(2201001)(26005)(186003)(575784001)(86362001)(104016004); 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BN1PR12MB0019; 20:LuguHQaKOypj8QepK6hfBn6JVuWyiFM13RtjkLuIgt7/3ar3BnHx0/y26Xklqa8c67SZkJLqOFYr01tBYQpZRZMQ4slELjBCgZLu7P1S2d0gUZko4CFcK4BbWLWeaEYI/5C3mXAZF8jFiJ0H3Mx3aA2OGq7Hi0vlxeXS5UU3pb+dIT/KQNIymrPw/Q52iH0wUoPVw7X94fxp2cd2XtX5zZygz3xBa181ZvKMGpzB5ox8eP8x7mmS48JXYOBZuvmL X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2018 06:32:36.7320 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1469b6ec-65ae-49a6-bcda-08d587e30bf0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXCHOV02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1PR12MB0019 Cc: tiwai@suse.de, Alexander.Deucher@amd.com, lgirdwood@gmail.com, Vijendar Mukunda Subject: [alsa-devel] [PATCH 2/7] ASoC: amd: dma descriptor changes for BT I2S Instance X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP As Stoney has SRAM memory limitation ,to support playback & capture on both the I2S controller instances audio buffer size is reduced to 8k. For playback on I2S SP instance sram bank 1 will be used. For capture on I2S SP instance sram bank 2 will be used. For playback on I2S BT instance sram bank 3 will be used. For capture on I2S BT instance sram bank 4 will be used. Signed-off-by: Vijendar Mukunda Reviewed-by: Alex Deucher --- sound/soc/amd/acp-pcm-dma.c | 106 ++++++++++++++++++++++++++++++++++---------- sound/soc/amd/acp.h | 41 +++++++++++++++-- 2 files changed, 120 insertions(+), 27 deletions(-) diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c index 4611706..f401006 100644 --- a/sound/soc/amd/acp-pcm-dma.c +++ b/sound/soc/amd/acp-pcm-dma.c @@ -37,7 +37,7 @@ #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) #define MIN_BUFFER MAX_BUFFER -#define ST_PLAYBACK_MAX_PERIOD_SIZE 8192 +#define ST_PLAYBACK_MAX_PERIOD_SIZE 4096 #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) #define ST_MIN_BUFFER ST_MAX_BUFFER @@ -320,42 +320,99 @@ static void config_acp_dma(void __iomem *acp_mmio, u16 ch1, ch2, destination, dma_dscr_idx; if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) { - pte_offset = ACP_PLAYBACK_PTE_OFFSET; - ch1 = SYSRAM_TO_ACP_CH_NUM; - ch2 = ACP_TO_I2S_DMA_CH_NUM; - sram_bank = ACP_SHARED_RAM_BANK_1_ADDRESS; - destination = TO_ACP_I2S_1; - - } else { - pte_offset = ACP_CAPTURE_PTE_OFFSET; - ch1 = SYSRAM_TO_ACP_CH_NUM; - ch2 = ACP_TO_I2S_DMA_CH_NUM; - switch (asic_type) { - case CHIP_STONEY: + switch (audio_config->i2s_play_instance) { + case I2S_BT_INSTANCE: + pte_offset = ACP_ST_I2S_BT_PLAYBACK_PTE_OFFSET; + ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM; + ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM; sram_bank = ACP_SHARED_RAM_BANK_3_ADDRESS; + destination = TO_BLUETOOTH; break; + case I2S_SP_INSTANCE: default: - sram_bank = ACP_SHARED_RAM_BANK_5_ADDRESS; + switch (asic_type) { + case CHIP_STONEY: + pte_offset = ACP_ST_I2S_SP_PLAYBACK_PTE_OFFSET; + break; + default: + pte_offset = ACP_PLAYBACK_PTE_OFFSET; + } + ch1 = SYSRAM_TO_ACP_CH_NUM; + ch2 = ACP_TO_I2S_DMA_CH_NUM; + sram_bank = ACP_SHARED_RAM_BANK_1_ADDRESS; + destination = TO_ACP_I2S_1; + } + } else { + switch (audio_config->i2s_capture_instance) { + case I2S_BT_INSTANCE: + pte_offset = ACP_ST_I2S_BT_CAPTURE_PTE_OFFSET; + ch1 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM; + ch2 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM; + sram_bank = ACP_SHARED_RAM_BANK_4_ADDRESS; + destination = FROM_BLUETOOTH; + break; + case I2S_SP_INSTANCE: + default: + pte_offset = ACP_CAPTURE_PTE_OFFSET; + ch1 = SYSRAM_TO_ACP_CH_NUM; + ch2 = ACP_TO_I2S_DMA_CH_NUM; + switch (asic_type) { + case CHIP_STONEY: + sram_bank = ACP_SHARED_RAM_BANK_2_ADDRESS; + break; + default: + sram_bank = ACP_SHARED_RAM_BANK_5_ADDRESS; + } + destination = FROM_ACP_I2S_1; } - destination = FROM_ACP_I2S_1; } acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages, pte_offset); - if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) - dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; - else - dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14; + if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) { + switch (audio_config->i2s_play_instance) { + case I2S_BT_INSTANCE: + dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH8; + break; + case I2S_SP_INSTANCE: + default: + dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; + } + } else { + switch (audio_config->i2s_capture_instance) { + case I2S_BT_INSTANCE: + dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH10; + break; + case I2S_SP_INSTANCE: + default: + dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14; + } + } /* Configure System memory <-> ACP SRAM DMA descriptors */ set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size, audio_config->direction, pte_offset, ch1, sram_bank, dma_dscr_idx, asic_type); - if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) - dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; - else - dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15; + if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) { + switch (audio_config->i2s_play_instance) { + case I2S_BT_INSTANCE: + dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH9; + break; + case I2S_SP_INSTANCE: + default: + dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; + } + } else { + switch (audio_config->i2s_capture_instance) { + case I2S_BT_INSTANCE: + dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH11; + break; + case I2S_SP_INSTANCE: + default: + dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15; + } + } /* Configure ACP SRAM <-> I2S DMA descriptors */ set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size, audio_config->direction, sram_bank, @@ -385,6 +442,9 @@ static void acp_dma_start(void __iomem *acp_mmio, case ACP_TO_I2S_DMA_CH_NUM: case ACP_TO_SYSRAM_CH_NUM: case I2S_TO_ACP_DMA_CH_NUM: + case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM: + case ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM: + case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM: dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; break; default: diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h index e8406b9..d40749a 100644 --- a/sound/soc/amd/acp.h +++ b/sound/soc/amd/acp.h @@ -10,17 +10,29 @@ #define ACP_PLAYBACK_PTE_OFFSET 10 #define ACP_CAPTURE_PTE_OFFSET 0 +/* Playback and Capture Offset for Stoney */ +#define ACP_ST_I2S_SP_PLAYBACK_PTE_OFFSET 0x04 +#define ACP_ST_I2S_SP_CAPTURE_PTE_OFFSET 0x00 +#define ACP_ST_I2S_BT_PLAYBACK_PTE_OFFSET 0x08 +#define ACP_ST_I2S_BT_CAPTURE_PTE_OFFSET 0x0c + #define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4 #define ACP_ONION_CNTL_DEFAULT 0x00000FB4 #define ACP_PHYSICAL_BASE 0x14000 -/* Playback SRAM address (as a destination in dma descriptor) */ +/* In case of I2S SP controller instance, Stoney uses SRAM bank 1 for + * playback and SRAM Bank 2 for capture where as in case of BT I2S + * Instance ,Stoney uses SRAM Bank 3 for playback & SRAM Bank 4 will + * be used for capture.Carrizo uses I2S SP controller instance.SRAM Banks + * 1,2,3,4 will be used for playback & SRAM Banks 5,6,7,8 will be used + * for capture scenario. + */ #define ACP_SHARED_RAM_BANK_1_ADDRESS 0x4002000 - -/* Capture SRAM address (as a source in dma descriptor) */ -#define ACP_SHARED_RAM_BANK_5_ADDRESS 0x400A000 +#define ACP_SHARED_RAM_BANK_2_ADDRESS 0x4004000 #define ACP_SHARED_RAM_BANK_3_ADDRESS 0x4006000 +#define ACP_SHARED_RAM_BANK_4_ADDRESS 0x4008000 +#define ACP_SHARED_RAM_BANK_5_ADDRESS 0x400A000 #define ACP_DMA_RESET_TIME 10000 #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF @@ -35,8 +47,10 @@ #define TO_ACP_I2S_1 0x2 #define TO_ACP_I2S_2 0x4 +#define TO_BLUETOOTH 0x3 #define FROM_ACP_I2S_1 0xa #define FROM_ACP_I2S_2 0xb +#define FROM_BLUETOOTH 0xb #define ACP_TILE_ON_MASK 0x03 #define ACP_TILE_OFF_MASK 0x02 @@ -57,6 +71,14 @@ #define ACP_TO_SYSRAM_CH_NUM 14 #define I2S_TO_ACP_DMA_CH_NUM 15 +/* Playback DMA Channels for I2S BT instance */ +#define SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM 8 +#define ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM 9 + +/* Capture DMA Channels for I2S BT Instance */ +#define ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM 10 +#define I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM 11 + #define NUM_DSCRS_PER_CHANNEL 2 #define PLAYBACK_START_DMA_DESCR_CH12 0 @@ -69,6 +91,17 @@ #define CAPTURE_START_DMA_DESCR_CH15 6 #define CAPTURE_END_DMA_DESCR_CH15 7 +/* I2S BT Instance DMA Descriptors */ +#define PLAYBACK_START_DMA_DESCR_CH8 8 +#define PLAYBACK_END_DMA_DESCR_CH8 9 +#define PLAYBACK_START_DMA_DESCR_CH9 10 +#define PLAYBACK_END_DMA_DESCR_CH9 11 + +#define CAPTURE_START_DMA_DESCR_CH10 12 +#define CAPTURE_END_DMA_DESCR_CH10 13 +#define CAPTURE_START_DMA_DESCR_CH11 14 +#define CAPTURE_END_DMA_DESCR_CH11 15 + #define mmACP_I2S_16BIT_RESOLUTION_EN 0x5209 #define ACP_I2S_MIC_16BIT_RESOLUTION_EN 0x01 #define ACP_I2S_SP_16BIT_RESOLUTION_EN 0x02