[4/7] ASoC: amd: prepare callback modifications for bt i2s instance

Commit Message

Mukunda,Vijendar March 12, 2018, 6:34 a.m. UTC

modified prepare callback for configuring dma channels for BT instance.

Signed-off-by: Vijendar Mukunda <[e-mail]>
---
 sound/soc/amd/acp-pcm-dma.c | 53 +++++++++++++++++++++++++++++++++++----------
 1 file changed, 41 insertions(+), 12 deletions(-)

Patch

diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index 8660f36..2b6c9ad 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -1014,25 +1014,54 @@  static int acp_dma_mmap(struct snd_pcm_substream *substream,
 
 static int acp_dma_prepare(struct snd_pcm_substream *substream)
 {
+	u16 start_dscr_idx;
 	struct snd_pcm_runtime *runtime = substream->runtime;
 	struct audio_substream_data *rtd = runtime->private_data;
 
 	if (!rtd)
 		return -EINVAL;
 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM,
-					PLAYBACK_START_DMA_DESCR_CH12,
-					NUM_DSCRS_PER_CHANNEL, 0);
-		config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM,
-					PLAYBACK_START_DMA_DESCR_CH13,
-					NUM_DSCRS_PER_CHANNEL, 0);
+		switch (rtd->i2s_play_instance) {
+		case I2S_BT_INSTANCE:
+			start_dscr_idx =  PLAYBACK_START_DMA_DESCR_CH8;
+			config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM,
+						start_dscr_idx,
+						NUM_DSCRS_PER_CHANNEL, 0);
+			config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM,
+						start_dscr_idx + 2,
+						NUM_DSCRS_PER_CHANNEL, 0);
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			start_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
+			config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM,
+						start_dscr_idx,
+						NUM_DSCRS_PER_CHANNEL, 0);
+			config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM,
+						start_dscr_idx + 2,
+						NUM_DSCRS_PER_CHANNEL, 0);
+		}
 	} else {
-		config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM,
-					CAPTURE_START_DMA_DESCR_CH14,
-					NUM_DSCRS_PER_CHANNEL, 0);
-		config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM,
-					CAPTURE_START_DMA_DESCR_CH15,
-					NUM_DSCRS_PER_CHANNEL, 0);
+		switch (rtd->i2s_capture_instance) {
+		case I2S_BT_INSTANCE:
+			start_dscr_idx = CAPTURE_START_DMA_DESCR_CH10;
+			config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
+						start_dscr_idx,
+						NUM_DSCRS_PER_CHANNEL, 0);
+			config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM,
+						start_dscr_idx + 2,
+						NUM_DSCRS_PER_CHANNEL, 0);
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			start_dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
+			config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM,
+						start_dscr_idx,
+						NUM_DSCRS_PER_CHANNEL, 0);
+			config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM,
+						start_dscr_idx + 2,
+						NUM_DSCRS_PER_CHANNEL, 0);
+		}
 	}
 	return 0;
 }