| Message ID | 1524741374-13523-9-git-send-email-Vijendar.Mukunda@amd.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 6e554074955b453e8c8d671ec523d273703f2a59 |
| Headers | show |
On Thu, Apr 26, 2018 at 5:17 AM Vijendar Mukunda <Vijendar.Mukunda@amd.com> wrote: > From: Akshu Agrawal <akshu.agrawal@amd.com> > System clock on the platform is 25Mhz and not 24Mhz. > PLL_OUT for da7219 codec to use DA7219_PLL_FREQ_OUT_98304 > as it is for 48KHz SR. > Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> > Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > --- > sound/soc/amd/acp-da7219-max98357a.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > diff --git a/sound/soc/amd/acp-da7219-max98357a.c b/sound/soc/amd/acp-da7219-max98357a.c > index 6495eed..fa5ad5b 100644 > --- a/sound/soc/amd/acp-da7219-max98357a.c > +++ b/sound/soc/amd/acp-da7219-max98357a.c > @@ -39,8 +39,7 @@ > #include "../codecs/da7219.h" > #include "../codecs/da7219-aad.h" > -#define CZ_PLAT_CLK 24000000 > -#define MCLK_RATE 24576000 > +#define CZ_PLAT_CLK 25000000 > #define DUAL_CHANNEL 2 > static struct snd_soc_jack cz_jack; > @@ -63,7 +62,7 @@ static int cz_da7219_init(struct snd_soc_pcm_runtime *rtd) > } > ret = snd_soc_dai_set_pll(codec_dai, 0, DA7219_SYSCLK_PLL, > - CZ_PLAT_CLK, MCLK_RATE); > + CZ_PLAT_CLK, DA7219_PLL_FREQ_OUT_98304); > if (ret < 0) { > dev_err(rtd->dev, "can't set codec pll: %d\n", ret); > return ret; > -- > 2.7.4
diff --git a/sound/soc/amd/acp-da7219-max98357a.c b/sound/soc/amd/acp-da7219-max98357a.c index 6495eed..fa5ad5b 100644 --- a/sound/soc/amd/acp-da7219-max98357a.c +++ b/sound/soc/amd/acp-da7219-max98357a.c @@ -39,8 +39,7 @@ #include "../codecs/da7219.h" #include "../codecs/da7219-aad.h" -#define CZ_PLAT_CLK 24000000 -#define MCLK_RATE 24576000 +#define CZ_PLAT_CLK 25000000 #define DUAL_CHANNEL 2 static struct snd_soc_jack cz_jack; @@ -63,7 +62,7 @@ static int cz_da7219_init(struct snd_soc_pcm_runtime *rtd) } ret = snd_soc_dai_set_pll(codec_dai, 0, DA7219_SYSCLK_PLL, - CZ_PLAT_CLK, MCLK_RATE); + CZ_PLAT_CLK, DA7219_PLL_FREQ_OUT_98304); if (ret < 0) { dev_err(rtd->dev, "can't set codec pll: %d\n", ret); return ret;