@@ -83,9 +83,20 @@ static int acp3x_i2s_hwparams(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
- u32 val = 0;
+ u32 val;
+ u32 reg_val;
+ struct snd_soc_pcm_runtime *prtd = substream->private_data;
+ struct snd_soc_card *card = prtd->card;
+ struct acp3x_platform_info *pinfo = snd_soc_card_get_drvdata(card);
struct i2s_stream_instance *rtd = substream->runtime->private_data;
+ if (pinfo) {
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ rtd->i2s_instance = pinfo->play_i2s_instance;
+ else
+ rtd->i2s_instance = pinfo->cap_i2s_instance;
+ }
+
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_U8:
case SNDRV_PCM_FORMAT_S8:
@@ -104,24 +115,46 @@ static int acp3x_i2s_hwparams(struct snd_pcm_substream *substream,
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER);
- val = val | (rtd->xfer_resolution << 3);
- rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER);
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ reg_val = mmACP_BTTDM_ITER;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ reg_val = mmACP_I2STDM_ITER;
+ }
} else {
- val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER);
- val = val | (rtd->xfer_resolution << 3);
- rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER);
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ reg_val = mmACP_BTTDM_IRER;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ reg_val = mmACP_I2STDM_IRER;
+ }
}
+ val = rv_readl(rtd->acp3x_base + reg_val);
+ val = val | (rtd->xfer_resolution << 3);
+ rv_writel(val, rtd->acp3x_base + reg_val);
return 0;
}
static int acp3x_i2s_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
- int ret = 0;
+ int ret;
struct i2s_stream_instance *rtd = substream->runtime->private_data;
- u32 val, period_bytes;
-
+ u32 val, period_bytes, reg_val, ier_val, water_val;
+ struct snd_soc_pcm_runtime *prtd = substream->private_data;
+ struct snd_soc_card *card = prtd->card;
+ struct acp3x_platform_info *pinfo = snd_soc_card_get_drvdata(card);
+
+ if (pinfo) {
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ rtd->i2s_instance = pinfo->play_i2s_instance;
+ else
+ rtd->i2s_instance = pinfo->cap_i2s_instance;
+ }
period_bytes = frames_to_bytes(substream->runtime,
substream->runtime->period_size);
switch (cmd) {
@@ -131,33 +164,73 @@ static int acp3x_i2s_trigger(struct snd_pcm_substream *substream,
rtd->bytescount = acp_get_byte_count(rtd,
substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- rv_writel(period_bytes, rtd->acp3x_base +
- mmACP_BT_TX_INTR_WATERMARK_SIZE);
- val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER);
- val = val | BIT(0);
- rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER);
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ water_val =
+ mmACP_BT_TX_INTR_WATERMARK_SIZE;
+ reg_val = mmACP_BTTDM_ITER;
+ ier_val = mmACP_BTTDM_IER;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ water_val =
+ mmACP_I2S_TX_INTR_WATERMARK_SIZE;
+ reg_val = mmACP_I2STDM_ITER;
+ ier_val = mmACP_I2STDM_IER;
+ }
} else {
- rv_writel(period_bytes, rtd->acp3x_base +
- mmACP_BT_RX_INTR_WATERMARK_SIZE);
- val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER);
- val = val | BIT(0);
- rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER);
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ water_val =
+ mmACP_BT_RX_INTR_WATERMARK_SIZE;
+ reg_val = mmACP_BTTDM_IRER;
+ ier_val = mmACP_BTTDM_IER;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ water_val =
+ mmACP_I2S_RX_INTR_WATERMARK_SIZE;
+ reg_val = mmACP_I2STDM_IRER;
+ ier_val = mmACP_I2STDM_IER;
+ }
}
- rv_writel(1, rtd->acp3x_base + mmACP_BTTDM_IER);
+ rv_writel(period_bytes, rtd->acp3x_base + water_val);
+ val = rv_readl(rtd->acp3x_base + reg_val);
+ val = val | BIT(0);
+ rv_writel(val, rtd->acp3x_base + reg_val);
+ rv_writel(1, rtd->acp3x_base + ier_val);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER);
- val = val & ~BIT(0);
- rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER);
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ reg_val = mmACP_BTTDM_ITER;
+ ier_val = mmACP_BTTDM_IER;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ reg_val = mmACP_I2STDM_ITER;
+ ier_val = mmACP_I2STDM_IER;
+ }
+
} else {
- val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER);
- val = val & ~BIT(0);
- rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER);
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ reg_val = mmACP_BTTDM_IRER;
+ ier_val = mmACP_BTTDM_IER;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ reg_val = mmACP_I2STDM_IRER;
+ ier_val = mmACP_I2STDM_IER;
+ }
}
- rv_writel(0, rtd->acp3x_base + mmACP_BTTDM_IER);
+ val = rv_readl(rtd->acp3x_base + reg_val);
+ val = val & ~BIT(0);
+ rv_writel(val, rtd->acp3x_base + reg_val);
+ rv_writel(0, rtd->acp3x_base + ier_val);
break;
default:
ret = -EINVAL;
@@ -193,20 +193,36 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction)
{
u16 page_idx;
- u32 low, high, val, acp_fifo_addr;
- dma_addr_t addr = rtd->dma_addr;
+ uint64_t low, high, val, acp_fifo_addr;
+ uint64_t reg_ringbuf_size, reg_dma_size, reg_fifo_size, reg_fifo_addr;
+ dma_addr_t addr;
- /* 8 scratch registers used to map one 64 bit address */
- if (direction == SNDRV_PCM_STREAM_PLAYBACK)
- val = 0;
- else
- val = rtd->num_pages * 8;
+ addr = rtd->dma_addr;
+ if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ val = ACP_SRAM_BT_PB_PTE_OFFSET;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ val = ACP_SRAM_SP_PB_PTE_OFFSET;
+ }
+ } else {
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ val = ACP_SRAM_BT_CP_PTE_OFFSET;
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ val = ACP_SRAM_SP_CP_PTE_OFFSET;
+ }
+ }
/* Group Enable */
rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base +
- mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
+ mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
rv_writel(PAGE_SIZE_4K_ENABLE, rtd->acp3x_base +
- mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
+ mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
@@ -223,38 +239,61 @@ static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction)
}
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
- /* Config ringbuffer */
- rv_writel(MEM_WINDOW_START, rtd->acp3x_base +
- mmACP_BT_TX_RINGBUFADDR);
- rv_writel(MAX_BUFFER, rtd->acp3x_base +
- mmACP_BT_TX_RINGBUFSIZE);
- rv_writel(DMA_SIZE, rtd->acp3x_base + mmACP_BT_TX_DMA_SIZE);
-
- /* Config audio fifo */
- acp_fifo_addr = ACP_SRAM_PTE_OFFSET + (rtd->num_pages * 8)
- + PLAYBACK_FIFO_ADDR_OFFSET;
- rv_writel(acp_fifo_addr, rtd->acp3x_base +
- mmACP_BT_TX_FIFOADDR);
- rv_writel(FIFO_SIZE, rtd->acp3x_base + mmACP_BT_TX_FIFOSIZE);
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ reg_ringbuf_size = mmACP_BT_TX_RINGBUFSIZE;
+ reg_dma_size = mmACP_BT_TX_DMA_SIZE;
+ acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+ BT_PB_FIFO_ADDR_OFFSET;
+ reg_fifo_addr = mmACP_BT_TX_FIFOADDR;
+ reg_fifo_size = mmACP_BT_TX_FIFOSIZE;
+ rv_writel(I2S_BT_TX_MEM_WINDOW_START,
+ rtd->acp3x_base + mmACP_BT_TX_RINGBUFADDR);
+ break;
+
+ case I2S_SP_INSTANCE:
+ default:
+ reg_ringbuf_size = mmACP_I2S_TX_RINGBUFSIZE;
+ reg_dma_size = mmACP_I2S_TX_DMA_SIZE;
+ acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+ SP_PB_FIFO_ADDR_OFFSET;
+ reg_fifo_addr = mmACP_I2S_TX_FIFOADDR;
+ reg_fifo_size = mmACP_I2S_TX_FIFOSIZE;
+ rv_writel(I2S_SP_TX_MEM_WINDOW_START,
+ rtd->acp3x_base + mmACP_I2S_TX_RINGBUFADDR);
+ }
} else {
- /* Config ringbuffer */
- rv_writel(MEM_WINDOW_START + MAX_BUFFER, rtd->acp3x_base +
- mmACP_BT_RX_RINGBUFADDR);
- rv_writel(MAX_BUFFER, rtd->acp3x_base +
- mmACP_BT_RX_RINGBUFSIZE);
- rv_writel(DMA_SIZE, rtd->acp3x_base + mmACP_BT_RX_DMA_SIZE);
-
- /* Config audio fifo */
- acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
- (rtd->num_pages * 8) + CAPTURE_FIFO_ADDR_OFFSET;
- rv_writel(acp_fifo_addr, rtd->acp3x_base +
- mmACP_BT_RX_FIFOADDR);
- rv_writel(FIFO_SIZE, rtd->acp3x_base + mmACP_BT_RX_FIFOSIZE);
- }
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ reg_ringbuf_size = mmACP_BT_RX_RINGBUFSIZE;
+ reg_dma_size = mmACP_BT_RX_DMA_SIZE;
+ acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+ BT_CAPT_FIFO_ADDR_OFFSET;
+ reg_fifo_addr = mmACP_BT_RX_FIFOADDR;
+ reg_fifo_size = mmACP_BT_RX_FIFOSIZE;
+ rv_writel(I2S_BT_RX_MEM_WINDOW_START,
+ rtd->acp3x_base + mmACP_BT_RX_RINGBUFADDR);
+ break;
- /* Enable watermark/period interrupt to host */
- rv_writel(BIT(BT_TX_THRESHOLD) | BIT(BT_RX_THRESHOLD),
- rtd->acp3x_base + mmACP_EXTERNAL_INTR_CNTL);
+ case I2S_SP_INSTANCE:
+ default:
+ reg_ringbuf_size = mmACP_I2S_RX_RINGBUFSIZE;
+ reg_dma_size = mmACP_I2S_RX_DMA_SIZE;
+ acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+ SP_CAPT_FIFO_ADDR_OFFSET;
+ reg_fifo_addr = mmACP_I2S_RX_FIFOADDR;
+ reg_fifo_size = mmACP_I2S_RX_FIFOSIZE;
+ rv_writel(I2S_SP_RX_MEM_WINDOW_START,
+ rtd->acp3x_base + mmACP_I2S_RX_RINGBUFADDR);
+ }
+ }
+ rv_writel(MAX_BUFFER, rtd->acp3x_base + reg_ringbuf_size);
+ rv_writel(DMA_SIZE, rtd->acp3x_base + reg_dma_size);
+ rv_writel(acp_fifo_addr, rtd->acp3x_base + reg_fifo_addr);
+ rv_writel(FIFO_SIZE, rtd->acp3x_base + reg_fifo_size);
+ rv_writel(BIT(I2S_RX_THRESHOLD) | BIT(BT_RX_THRESHOLD)
+ | BIT(I2S_TX_THRESHOLD) | BIT(BT_TX_THRESHOLD),
+ rtd->acp3x_base + mmACP_EXTERNAL_INTR_CNTL);
}
static int acp3x_dma_open(struct snd_soc_component *component,
@@ -284,13 +323,17 @@ static int acp3x_dma_open(struct snd_soc_component *component,
return ret;
}
- if (!adata->play_stream && !adata->capture_stream)
+ if (!adata->play_stream && !adata->capture_stream &&
+ adata->i2ssp_play_stream && !adata->i2ssp_capture_stream)
rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
adata->play_stream = substream;
- else
+ adata->i2ssp_play_stream = substream;
+ } else {
adata->capture_stream = substream;
+ adata->i2ssp_capture_stream = substream;
+ }
i2s_data->acp3x_base = adata->acp3x_base;
runtime->private_data = i2s_data;
@@ -303,13 +346,24 @@ static int acp3x_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
int status;
- u64 size;
- struct snd_pcm_runtime *runtime = substream->runtime;
- struct i2s_stream_instance *rtd = runtime->private_data;
+ uint64_t size;
+ struct snd_soc_pcm_runtime *prtd = substream->private_data;
+ struct snd_soc_card *card = prtd->card;
+ struct acp3x_platform_info *pinfo = snd_soc_card_get_drvdata(card);
+ struct i2s_stream_instance *rtd = substream->runtime->private_data;
if (!rtd)
return -EINVAL;
+
+ if (pinfo) {
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ rtd->i2s_instance = pinfo->play_i2s_instance;
+ else
+ rtd->i2s_instance = pinfo->cap_i2s_instance;
+ } else
+ pr_err("pinfo failed\n");
+
size = params_buffer_bytes(params);
status = snd_pcm_lib_malloc_pages(substream, size);
if (status < 0)
@@ -333,8 +387,17 @@ static snd_pcm_uframes_t acp3x_dma_pointer(struct snd_soc_component *component,
u32 pos = 0;
u32 buffersize = 0;
u64 bytescount = 0;
- struct i2s_stream_instance *rtd =
- substream->runtime->private_data;
+ struct snd_soc_pcm_runtime *prtd = substream->private_data;
+ struct snd_soc_card *card = prtd->card;
+ struct acp3x_platform_info *pinfo = snd_soc_card_get_drvdata(card);
+ struct i2s_stream_instance *rtd = substream->runtime->private_data;
+
+ if (pinfo) {
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ rtd->i2s_instance = pinfo->play_i2s_instance;
+ else
+ rtd->i2s_instance = pinfo->cap_i2s_instance;
+ }
buffersize = frames_to_bytes(substream->runtime,
substream->runtime->buffer_size);
@@ -376,15 +439,19 @@ static int acp3x_dma_close(struct snd_soc_component *component,
component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
struct i2s_dev_data *adata = dev_get_drvdata(component->dev);
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
adata->play_stream = NULL;
- else
+ adata->i2ssp_play_stream = NULL;
+ } else {
adata->capture_stream = NULL;
+ adata->i2ssp_capture_stream = NULL;
+ }
/* Disable ACP irq, when the current stream is being closed and
* another stream is also not active.
*/
- if (!adata->play_stream && !adata->capture_stream)
+ if (!adata->play_stream && !adata->capture_stream &&
+ !adata->i2ssp_play_stream && !adata->i2ssp_capture_stream)
rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
kfree(rtd);
return 0;
@@ -518,13 +585,16 @@ static int acp3x_resume(struct device *dev)
adata->play_stream->runtime->private_data;
config_acp3x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
rv_writel((rtd->xfer_resolution << 3),
- rtd->acp3x_base + mmACP_BTTDM_ITER);
+ rtd->acp3x_base + mmACP_BTTDM_ITER);
+ val = rv_readl(rtd->acp3x_base + mmACP_I2STDM_ITER);
+ val = val | (rtd->xfer_resolution << 3);
+ rv_writel(val, rtd->acp3x_base + mmACP_I2STDM_ITER);
if (adata->tdm_mode == true) {
rv_writel(adata->tdm_fmt, adata->acp3x_base +
- mmACP_BTTDM_TXFRMT);
+ mmACP_BTTDM_TXFRMT);
val = rv_readl(adata->acp3x_base + mmACP_BTTDM_ITER);
rv_writel((val | 0x2), adata->acp3x_base +
- mmACP_BTTDM_ITER);
+ mmACP_BTTDM_ITER);
}
}
@@ -533,13 +603,17 @@ static int acp3x_resume(struct device *dev)
adata->capture_stream->runtime->private_data;
config_acp3x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
rv_writel((rtd->xfer_resolution << 3),
- rtd->acp3x_base + mmACP_BTTDM_IRER);
+ rtd->acp3x_base + mmACP_BTTDM_IRER);
+ val = rv_readl(rtd->acp3x_base + mmACP_I2STDM_ITER);
+ val = val | (rtd->xfer_resolution << 3);
+ rv_writel(val, rtd->acp3x_base + mmACP_I2STDM_ITER);
+
if (adata->tdm_mode == true) {
rv_writel(adata->tdm_fmt, adata->acp3x_base +
- mmACP_BTTDM_RXFRMT);
+ mmACP_BTTDM_RXFRMT);
val = rv_readl(adata->acp3x_base + mmACP_BTTDM_IRER);
rv_writel((val | 0x2), adata->acp3x_base +
- mmACP_BTTDM_IRER);
+ mmACP_BTTDM_IRER);
}
}
@@ -7,6 +7,9 @@
#include "chip_offset_byte.h"
+#define I2S_SP_INSTANCE 0x01
+#define I2S_BT_INSTANCE 0x02
+
#define ACP3x_DEVS 3
#define ACP3x_PHY_BASE_ADDRESS 0x1240000
#define ACP3x_I2S_MODE 0
@@ -17,8 +20,11 @@
#define ACP3x_BT_TDM_REG_START 0x1242800
#define ACP3x_BT_TDM_REG_END 0x1242810
#define I2S_MODE 0x04
+#define I2S_RX_THRESHOLD 27
+#define I2S_TX_THRESHOLD 28
#define BT_TX_THRESHOLD 26
#define BT_RX_THRESHOLD 25
+#define ACP_ERR_INTR_MASK 29
#define ACP3x_POWER_ON 0x00
#define ACP3x_POWER_ON_IN_PROGRESS 0x01
#define ACP3x_POWER_OFF 0x02
@@ -26,19 +32,28 @@
#define ACP3x_SOFT_RESET__SoftResetAudDone_MASK 0x00010001
#define ACP_SRAM_PTE_OFFSET 0x02050000
+#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
+#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
+#define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
+#define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
#define PAGE_SIZE_4K_ENABLE 0x2
-#define MEM_WINDOW_START 0x4000000
-#define PLAYBACK_FIFO_ADDR_OFFSET 0x400
-#define CAPTURE_FIFO_ADDR_OFFSET 0x500
+#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
+#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
+#define I2S_BT_TX_MEM_WINDOW_START 0x4040000
+#define I2S_BT_RX_MEM_WINDOW_START 0x4060000
+#define SP_PB_FIFO_ADDR_OFFSET 0x500
+#define SP_CAPT_FIFO_ADDR_OFFSET 0x700
+#define BT_PB_FIFO_ADDR_OFFSET 0x900
+#define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
#define PLAYBACK_MIN_NUM_PERIODS 2
#define PLAYBACK_MAX_NUM_PERIODS 8
-#define PLAYBACK_MAX_PERIOD_SIZE 16384
-#define PLAYBACK_MIN_PERIOD_SIZE 4096
+#define PLAYBACK_MAX_PERIOD_SIZE 8192
+#define PLAYBACK_MIN_PERIOD_SIZE 1024
#define CAPTURE_MIN_NUM_PERIODS 2
#define CAPTURE_MAX_NUM_PERIODS 8
-#define CAPTURE_MAX_PERIOD_SIZE 16384
-#define CAPTURE_MIN_PERIOD_SIZE 4096
+#define CAPTURE_MAX_PERIOD_SIZE 8192
+#define CAPTURE_MIN_PERIOD_SIZE 1024
#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
#define MIN_BUFFER MAX_BUFFER
@@ -64,14 +79,20 @@ struct i2s_dev_data {
void __iomem *acp3x_base;
struct snd_pcm_substream *play_stream;
struct snd_pcm_substream *capture_stream;
+ struct snd_pcm_substream *i2ssp_play_stream;
+ struct snd_pcm_substream *i2ssp_capture_stream;
};
struct i2s_stream_instance {
u16 num_pages;
+ u16 i2s_instance;
+ u16 capture_channel;
+ u16 direction;
u16 channels;
u32 xfer_resolution;
- u64 bytescount;
+ u32 val;
dma_addr_t dma_addr;
+ u64 bytescount;
void __iomem *acp3x_base;
};
@@ -91,15 +112,36 @@ static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
u64 byte_count;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
- byte_count = rv_readl(rtd->acp3x_base +
- mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
- byte_count |= rv_readl(rtd->acp3x_base +
- mmACP_BT_TX_LINEARPOSITIONCNTR_LOW);
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ byte_count = rv_readl(rtd->acp3x_base +
+ mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
+ byte_count |= rv_readl(rtd->acp3x_base +
+ mmACP_BT_TX_LINEARPOSITIONCNTR_LOW);
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ byte_count = rv_readl(rtd->acp3x_base +
+ mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
+ byte_count |= rv_readl(rtd->acp3x_base +
+ mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
+ }
+
} else {
- byte_count = rv_readl(rtd->acp3x_base +
- mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
- byte_count |= rv_readl(rtd->acp3x_base +
- mmACP_BT_RX_LINEARPOSITIONCNTR_LOW);
+ switch (rtd->i2s_instance) {
+ case I2S_BT_INSTANCE:
+ byte_count = rv_readl(rtd->acp3x_base +
+ mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
+ byte_count |= rv_readl(rtd->acp3x_base +
+ mmACP_BT_RX_LINEARPOSITIONCNTR_LOW);
+ break;
+ case I2S_SP_INSTANCE:
+ default:
+ byte_count = rv_readl(rtd->acp3x_base +
+ mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
+ byte_count |= rv_readl(rtd->acp3x_base +
+ mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
+ }
}
return byte_count;
}
This patch adds I2S SP support in ACP PCM DMA and DAI. Added I2S support in DMA and DAI probe,its hw_params handling its open and close functionalities. This enable to open and close on the SP instance for playback and capture. Signed-off-by: Ravulapati Vishnu vardhan rao <Vishnuvardhanrao.Ravulapati@amd.com> --- sound/soc/amd/raven/acp3x-i2s.c | 129 +++++++++++++++++++------ sound/soc/amd/raven/acp3x-pcm-dma.c | 186 +++++++++++++++++++++++++----------- sound/soc/amd/raven/acp3x.h | 74 ++++++++++---- 3 files changed, 289 insertions(+), 100 deletions(-)