| Message ID | 1616150926-22892-1-git-send-email-shengjiu.wang@nxp.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 16b82e75c15a7dbd564ea3654f3feb61df9e1e6f |
| Headers | show |
| Series | ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips | expand |
On Fri, Mar 19, 2021 at 06:48:46PM +0800, Shengjiu Wang wrote: > The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz > and sample rate is 44100Hz, with the configuration pllprescale=2, > postscale=sysclkdiv=1, some chip may have wrong bclk > and lrclk output with pll enabled in master mode, but with the > configuration pllprescale=1, postscale=2, the output clock is correct. > > >From Datasheet, the PLL performs best when f2 is between > 90MHz and 100MHz when the desired sysclk output is 11.2896MHz > or 12.288MHz, so sysclkdiv = 2 (f2/8) is the best choice. > > So search available sysclk_divs from 2 to 1 other than from 1 to 2. > > Fixes: 84fdc00d519f ("ASoC: codec: wm9860: Refactor PLL out freq search") > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> > --- Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Thanks, Charles
On Fri, 19 Mar 2021 18:48:46 +0800, Shengjiu Wang wrote: > The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz > and sample rate is 44100Hz, with the configuration pllprescale=2, > postscale=sysclkdiv=1, some chip may have wrong bclk > and lrclk output with pll enabled in master mode, but with the > configuration pllprescale=1, postscale=2, the output clock is correct. > > >From Datasheet, the PLL performs best when f2 is between > 90MHz and 100MHz when the desired sysclk output is 11.2896MHz > or 12.288MHz, so sysclkdiv = 2 (f2/8) is the best choice. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/1] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips commit: 16b82e75c15a7dbd564ea3654f3feb61df9e1e6f All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index df351519a3a6..cda9cd935d4f 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -707,7 +707,13 @@ int wm8960_configure_pll(struct snd_soc_component *component, int freq_in, best_freq_out = -EINVAL; *sysclk_idx = *dac_idx = *bclk_idx = -1; - for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) { + /* + * From Datasheet, the PLL performs best when f2 is between + * 90MHz and 100MHz, the desired sysclk output is 11.2896MHz + * or 12.288MHz, then sysclkdiv = 2 is the best choice. + * So search sysclk_divs from 2 to 1 other than from 1 to 2. + */ + for (i = ARRAY_SIZE(sysclk_divs) - 1; i >= 0; --i) { if (sysclk_divs[i] == -1) continue; for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz and sample rate is 44100Hz, with the configuration pllprescale=2, postscale=sysclkdiv=1, some chip may have wrong bclk and lrclk output with pll enabled in master mode, but with the configuration pllprescale=1, postscale=2, the output clock is correct. From Datasheet, the PLL performs best when f2 is between 90MHz and 100MHz when the desired sysclk output is 11.2896MHz or 12.288MHz, so sysclkdiv = 2 (f2/8) is the best choice. So search available sysclk_divs from 2 to 1 other than from 1 to 2. Fixes: 84fdc00d519f ("ASoC: codec: wm9860: Refactor PLL out freq search") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> --- sound/soc/codecs/wm8960.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)