From patchwork Sun Mar 5 13:37:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 9604593 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 14B7660414 for ; Sun, 5 Mar 2017 13:40:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 05D37283BC for ; Sun, 5 Mar 2017 13:40:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ED2D0283B3; Sun, 5 Mar 2017 13:40:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,T_DKIM_INVALID autolearn=no version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 43597283B3 for ; Sun, 5 Mar 2017 13:40:31 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 6589F266BED; Sun, 5 Mar 2017 14:40:27 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 748AF266C94; Sun, 5 Mar 2017 14:40:24 +0100 (CET) Received: from forward7h.cmail.yandex.net (forward7h.cmail.yandex.net [87.250.230.218]) by alsa0.perex.cz (Postfix) with ESMTP id ADEA0266C5D for ; Sun, 5 Mar 2017 14:39:39 +0100 (CET) Received: from smtp1m.mail.yandex.net (smtp1m.mail.yandex.net [IPv6:2a02:6b8:0:2519::121]) by forward7h.cmail.yandex.net (Yandex) with ESMTP id 78C0A22849; Sun, 5 Mar 2017 16:39:38 +0300 (MSK) Received: from smtp1m.mail.yandex.net (localhost.localdomain [127.0.0.1]) by smtp1m.mail.yandex.net (Yandex) with ESMTP id AF2FB63C0E1B; Sun, 5 Mar 2017 16:39:32 +0300 (MSK) Received: by smtp1m.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id 1xu4bs3MBZ-dPTmvA0W; Sun, 05 Mar 2017 16:39:31 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aosc.xyz; s=mail; t=1488721172; bh=bKu/Yb/doMPZhmWbufLXd8/8SvPCt7EFn+emlhlxAPI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Q9vj2ZP3yVyXyK1DMhm55lszIRPQp4Bqtt9VJNMlQO2+IIps2msAAJGOW0v67/I6L 3zecom7AzqviV8iauBp+UTYZ3CJ83OIe/vIVN+h1sqaTfnORNU8RUf28oKm3Xf7WhQ YDntz3PRsoUHVdsMntm/Gfie9SPExSTxmcW5Bx/4= Authentication-Results: smtp1m.mail.yandex.net; dkim=pass header.i=@aosc.xyz X-Yandex-ForeignMX: US X-Yandex-Suid-Status: 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 1130000036118848 From: Icenowy Zheng To: Vinod Koul , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Mark Brown Date: Sun, 5 Mar 2017 21:37:03 +0800 Message-Id: <20170305133709.6288-7-icenowy@aosc.xyz> X-Mailer: git-send-email 2.11.1 In-Reply-To: <20170305133709.6288-1-icenowy@aosc.xyz> References: <20170305133709.6288-1-icenowy@aosc.xyz> Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v2 06/12] dmaengine: sun6i: make gate bit in sun8i's DMA engines a common quirk X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Originally we enable a special gate bit when the compatible indicates A23/33. But according to BSP sources and user manuals, more SoCs will need this gate bit. So make it a common quirk configured in the config struct. The BSP source also indicates that A83T will need this gate bit (there's "SUN8IW6" in the #ifdef's), so also enable this gate bit for it. Signed-off-by: Icenowy Zheng Acked-by: Chen-Yu Tsai --- drivers/dma/sun6i-dma.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index a2358780ab2c..889fb24023cd 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -101,6 +101,7 @@ struct sun6i_dma_config { u32 nr_max_channels; u32 nr_max_requests; u32 nr_max_vchans; + bool gate_needed; }; /* @@ -1009,12 +1010,14 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .nr_max_channels = 8, .nr_max_requests = 24, .nr_max_vchans = 37, + .gate_needed = true, }; static struct sun6i_dma_config sun8i_a83t_dma_cfg = { .nr_max_channels = 8, .nr_max_requests = 28, .nr_max_vchans = 39, + .gate_needed = true, }; /* @@ -1177,10 +1180,10 @@ static int sun6i_dma_probe(struct platform_device *pdev) /* * sun8i variant requires us to toggle a dma gating register, * as seen in Allwinner's SDK. This register is not documented - * in the A23 user manual. + * in the A23 user manual, but documented at least in V3s user + * manual. */ - if (of_device_is_compatible(pdev->dev.of_node, - "allwinner,sun8i-a23-dma")) + if (sdc->cfg->gate_needed) writel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE); return 0;