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ASoC: Intel: Skylake: Reset stream to link mapping

Message ID 20180401094323.20864-1-sanyog.r.kale@intel.com (mailing list archive)
State Accepted
Commit 112c60b333ec9ddc7e940116f5e9fdc0d1a9706a
Headers show

Commit Message

Sanyog Kale April 1, 2018, 9:43 a.m. UTC 
From: Rakesh Ughreja <rakesh.a.ughreja@intel.com>

By default all the streams are mapped to all links after controller is
reset which causes stream to be broadcast on all the links.

This patch resets the stream-link mapping after controller reset. The
stream is mapped later to the appropriate link as part of stream setup.

Tested-by: Abhijeet Kumar <abhijeet.kumar@intel.com>
Signed-off-by: Rakesh Ughreja <rakesh.a.ughreja@intel.com>
Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com>
---
 sound/soc/intel/skylake/skl.c | 7 +++++++
 1 file changed, 7 insertions(+)
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Patch

diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
index abf324747b29..f0d9793f872a 100644
--- a/sound/soc/intel/skylake/skl.c
+++ b/sound/soc/intel/skylake/skl.c
@@ -127,10 +127,17 @@  static void skl_clock_power_gating(struct device *dev, bool enable)
  */
 static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
 {
+	struct hdac_ext_bus *ebus = hbus_to_ebus(bus);
+	struct hdac_ext_link *hlink;
 	int ret;
 
 	skl_enable_miscbdcge(bus->dev, false);
 	ret = snd_hdac_bus_init_chip(bus, full_reset);
+
+	/* Reset stream-to-link mapping */
+	list_for_each_entry(hlink, &ebus->hlink_list, list)
+		bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
+
 	skl_enable_miscbdcge(bus->dev, true);
 
 	return ret;