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[77.186.126.180]) by smtp.gmail.com with ESMTPSA id g24sm2866647edj.87.2018.04.03.21.19.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 03 Apr 2018 21:19:30 -0700 (PDT) From: Kirill Marinushkin To: Mark Brown Date: Wed, 4 Apr 2018 06:19:39 +0200 Message-Id: <20180404041939.23317-4-k.marinushkin@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180404041939.23317-1-k.marinushkin@gmail.com> References: <20180404041939.23317-1-k.marinushkin@gmail.com> Cc: alsa-devel@alsa-project.org, Takashi Iwai , Pan Xiuli , Pierre-Louis Bossart , linux-kernel@vger.kernel.org, Liam Girdwood , Kirill Marinushkin Subject: [alsa-devel] [PATCH v4 3/3] ASoC: topology: Add definitions for mclk_direction values X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Current comment makes not clear the direction of mclk. Previously, similar description caused a misunderstanding for bclk_master and fsync_master. This commit solves the potential confusion the same way it is solved for bclk_master and fsync_master. Signed-off-by: Kirill Marinushkin Acked-by: Pierre-Louis Bossart Cc: Jaroslav Kysela Cc: Takashi Iwai Cc: Mark Brown Cc: Pan Xiuli Cc: Liam Girdwood Cc: linux-kernel@vger.kernel.org Cc: alsa-devel@alsa-project.org --- include/uapi/sound/asoc.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/uapi/sound/asoc.h b/include/uapi/sound/asoc.h index f3c4b46e39d8..b901cdbe532a 100644 --- a/include/uapi/sound/asoc.h +++ b/include/uapi/sound/asoc.h @@ -144,6 +144,10 @@ #define SND_SOC_TPLG_DAI_CLK_GATE_GATED 1 #define SND_SOC_TPLG_DAI_CLK_GATE_CONT 2 +/* DAI mclk_direction */ +#define SND_SOC_TPLG_MCLK_CO 0 /* for codec, mclk is output */ +#define SND_SOC_TPLG_MCLK_CI 1 /* for codec, mclk is input */ + /* DAI physical PCM data formats. * Add new formats to the end of the list. */ @@ -334,7 +338,7 @@ struct snd_soc_tplg_hw_config { __u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */ __u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */ __u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */ - __u8 mclk_direction; /* 0 for input, 1 for output */ + __u8 mclk_direction; /* SND_SOC_TPLG_MCLK_ value */ __le16 reserved; /* for 32bit alignment */ __le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */ __le32 bclk_rate; /* BCLK freqency in Hz */