@@ -135,6 +135,11 @@
#define SND_SOC_TPLG_DAI_FLGBIT_SYMMETRIC_CHANNELS (1 << 1)
#define SND_SOC_TPLG_DAI_FLGBIT_SYMMETRIC_SAMPLEBITS (1 << 2)
+/* DAI clock gating */
+#define SND_SOC_TPLG_DAI_CLK_GATE_UNDEFINED 0
+#define SND_SOC_TPLG_DAI_CLK_GATE_GATED 1
+#define SND_SOC_TPLG_DAI_CLK_GATE_CONT 2
+
/* DAI physical PCM data formats.
* Add new formats to the end of the list.
*/
@@ -320,7 +325,7 @@ struct snd_soc_tplg_hw_config {
__le32 size; /* in bytes of this structure */
__le32 id; /* unique ID - - used to match */
__le32 fmt; /* SND_SOC_DAI_FORMAT_ format value */
- __u8 clock_gated; /* 1 if clock can be gated to save power */
+ __u8 clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */
__u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */
__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
__u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
@@ -997,7 +997,7 @@ struct snd_tplg_pcm_template {
struct snd_tplg_hw_config_template {
int id; /* unique ID - - used to match */
unsigned int fmt; /* SND_SOC_DAI_FORMAT_ format value */
- unsigned char clock_gated; /* 1 if clock can be gated to save power */
+ unsigned char clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */
unsigned char invert_bclk; /* 1 for inverted BCLK, 0 for normal */
unsigned char invert_fsync; /* 1 for inverted frame clock, 0 for normal */
unsigned char bclk_master; /* SND_SOC_TPLG_BCLK_ value */
@@ -1233,7 +1233,11 @@ int tplg_parse_hw_config(snd_tplg_t *tplg, snd_config_t *cfg,
return -EINVAL;
if (!strcmp(val, "true"))
- hw_cfg->clock_gated = true;
+ hw_cfg->clock_gated =
+ SND_SOC_TPLG_DAI_CLK_GATE_GATED;
+ else
+ hw_cfg->clock_gated =
+ SND_SOC_TPLG_DAI_CLK_GATE_CONT;
continue;
}