@@ -192,6 +192,25 @@ void skl_update_d0i3c(struct device *dev, bool enable)
snd_hdac_chip_readb(bus, VS_D0I3C));
}
+/**
+ * skl_dum_set - set DUM bit in EM2 register
+ * @bus: HD-audio core bus
+ *
+ * Addresses incorrect position reporting for capture streams.
+ * Used on device power up.
+ */
+static void skl_dum_set(struct hdac_bus *bus)
+{
+ /* For the DUM bit to be set, CRST needs to be out of reset state */
+ if (!(snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)) {
+ skl_enable_miscbdcge(bus->dev, false);
+ snd_hdac_bus_exit_link_reset(bus);
+ skl_enable_miscbdcge(bus->dev, true);
+ }
+
+ snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM);
+}
+
/* called from IRQ */
static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
{
@@ -299,6 +318,7 @@ static int _skl_resume(struct hdac_bus *bus)
struct skl *skl = bus_to_skl(bus);
skl_init_pci(skl);
+ skl_dum_set(bus);
skl_init_chip(bus, true);
return skl_resume_dsp(skl);
@@ -956,6 +976,7 @@ static int skl_first_init(struct hdac_bus *bus)
/* initialize chip */
skl_init_pci(skl);
+ skl_dum_set(bus);
return skl_init_chip(bus, true);
}
@@ -46,6 +46,7 @@
#define DMA_TRANSMITION_START 2
#define DMA_TRANSMITION_STOP 3
+#define AZX_VS_EM2_DUM BIT(23)
#define AZX_REG_VS_EM2_L1SEN BIT(13)
struct skl_dsp_resource {