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[213.102.65.51]) by smtp.gmail.com with ESMTPSA id j191sm1361493lfj.49.2019.10.16.00.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 00:07:44 -0700 (PDT) From: codekipper@gmail.com To: mripard@kernel.org, wens@csie.org, linux-sunxi@googlegroups.com Date: Wed, 16 Oct 2019 09:07:35 +0200 Message-Id: <20191016070740.121435-3-codekipper@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191016070740.121435-1-codekipper@gmail.com> References: <20191016070740.121435-1-codekipper@gmail.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, Marcus Cooper , lgirdwood@gmail.com, linux-kernel@vger.kernel.org, be17068@iperbole.bo.it, broonie@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v6 2/7] ASoC: sun4i-i2s: Add functions for RX and TX channel offsets X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Marcus Cooper Newer SoCs like the H6 have the channel offset bits in a different position to what is on the H3. As we will eventually add multi- channel support then create function calls as opposed to regmap fields to add support for different devices. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index f1a80973c450..875567881f30 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -157,6 +157,8 @@ struct sun4i_i2s_quirks { int (*set_chan_cfg)(const struct sun4i_i2s *, const struct snd_pcm_hw_params *); int (*set_fmt)(struct sun4i_i2s *, unsigned int); + void (*set_txchanoffset)(const struct sun4i_i2s *, int); + void (*set_rxchanoffset)(const struct sun4i_i2s *); }; struct sun4i_i2s { @@ -467,6 +469,23 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, return 0; } +static void sun8i_i2s_set_txchanoffset(const struct sun4i_i2s *i2s, int output) +{ + if (output >= 0 && output < 4) + regmap_update_bits(i2s->regmap, + SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4), + SUN8I_I2S_TX_CHAN_OFFSET_MASK, + SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); +} + +static void sun8i_i2s_set_rxchanoffset(const struct sun4i_i2s *i2s) +{ + regmap_update_bits(i2s->regmap, + SUN8I_I2S_RX_CHAN_SEL_REG, + SUN8I_I2S_TX_CHAN_OFFSET_MASK, + SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); +} + static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -661,12 +680,10 @@ static int sun8i_i2s_set_soc_fmt(struct sun4i_i2s *i2s, regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, SUN8I_I2S_CTRL_MODE_MASK, mode); - regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, - SUN8I_I2S_TX_CHAN_OFFSET_MASK, - SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); - regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, - SUN8I_I2S_TX_CHAN_OFFSET_MASK, - SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); + if (i2s->variant->set_txchanoffset) + i2s->variant->set_txchanoffset(i2s, 0); + if (i2s->variant->set_rxchanoffset) + i2s->variant->set_rxchanoffset(i2s); /* DAI clock master masks */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { @@ -1136,6 +1153,8 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { .get_wss = sun8i_i2s_get_sr_wss, .set_chan_cfg = sun8i_i2s_set_chan_cfg, .set_fmt = sun8i_i2s_set_soc_fmt, + .set_txchanoffset = sun8i_i2s_set_txchanoffset, + .set_rxchanoffset = sun8i_i2s_set_rxchanoffset, }; static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {