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[165.204.84.11]) by smtp.gmail.com with ESMTPSA id c26sm9148691qkm.98.2020.05.11.14.20.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2020 14:20:25 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: alsa-devel@alsa-project.org, broonie@kernel.org, vijendar.mukunda@amd.com, tiwai@suse.de Subject: [PATCH v2 02/14] ASoC: amd: add Renoir ACP PCI driver Date: Mon, 11 May 2020 17:20:02 -0400 Message-Id: <20200511212014.2359225-3-alexander.deucher@amd.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200511212014.2359225-1-alexander.deucher@amd.com> References: <20200511212014.2359225-1-alexander.deucher@amd.com> MIME-Version: 1.0 Cc: Alex Deucher , Vijendar Mukunda X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Vijendar Mukunda ACP is a PCI audio device. This patch adds PCI driver to bind to this device and get PCI resources. Signed-off-by: Vijendar Mukunda Signed-off-by: Alex Deucher --- sound/soc/amd/renoir/rn-pci-acp3x.c | 87 +++++++++++++++++++++++++++++ sound/soc/amd/renoir/rn_acp3x.h | 21 +++++++ 2 files changed, 108 insertions(+) create mode 100644 sound/soc/amd/renoir/rn-pci-acp3x.c create mode 100644 sound/soc/amd/renoir/rn_acp3x.h diff --git a/sound/soc/amd/renoir/rn-pci-acp3x.c b/sound/soc/amd/renoir/rn-pci-acp3x.c new file mode 100644 index 000000000000..56b76e355cd4 --- /dev/null +++ b/sound/soc/amd/renoir/rn-pci-acp3x.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// AMD Renoir ACP PCI Driver +// +//Copyright 2020 Advanced Micro Devices, Inc. + +#include +#include +#include + +#include "rn_acp3x.h" + +struct acp_dev_data { + void __iomem *acp_base; +}; + +static int snd_rn_acp_probe(struct pci_dev *pci, + const struct pci_device_id *pci_id) +{ + struct acp_dev_data *adata; + int ret; + u32 addr; + + if (pci_enable_device(pci)) { + dev_err(&pci->dev, "pci_enable_device failed\n"); + return -ENODEV; + } + + ret = pci_request_regions(pci, "AMD ACP3x audio"); + if (ret < 0) { + dev_err(&pci->dev, "pci_request_regions failed\n"); + goto disable_pci; + } + + adata = devm_kzalloc(&pci->dev, sizeof(struct acp_dev_data), + GFP_KERNEL); + if (!adata) { + ret = -ENOMEM; + goto release_regions; + } + + addr = pci_resource_start(pci, 0); + adata->acp_base = devm_ioremap(&pci->dev, addr, + pci_resource_len(pci, 0)); + if (!adata->acp_base) { + ret = -ENOMEM; + goto release_regions; + } + pci_set_master(pci); + pci_set_drvdata(pci, adata); + return 0; + +release_regions: + pci_release_regions(pci); +disable_pci: + pci_disable_device(pci); + + return ret; +} + +static void snd_rn_acp_remove(struct pci_dev *pci) +{ + pci_disable_msi(pci); + pci_release_regions(pci); + pci_disable_device(pci); +} + +static const struct pci_device_id snd_rn_acp_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID), + .class = PCI_CLASS_MULTIMEDIA_OTHER << 8, + .class_mask = 0xffffff }, + { 0, }, +}; +MODULE_DEVICE_TABLE(pci, snd_rn_acp_ids); + +static struct pci_driver rn_acp_driver = { + .name = KBUILD_MODNAME, + .id_table = snd_rn_acp_ids, + .probe = snd_rn_acp_probe, + .remove = snd_rn_acp_remove, +}; + +module_pci_driver(rn_acp_driver); + +MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); +MODULE_DESCRIPTION("AMD ACP Renoir PCI driver"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/amd/renoir/rn_acp3x.h b/sound/soc/amd/renoir/rn_acp3x.h new file mode 100644 index 000000000000..da5715759646 --- /dev/null +++ b/sound/soc/amd/renoir/rn_acp3x.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AMD ALSA SoC PDM Driver + * + * Copyright 2020 Advanced Micro Devices, Inc. + */ + +#include "rn_chip_offset_byte.h" + +#define ACP_PHY_BASE_ADDRESS 0x1240000 +#define ACP_DEVICE_ID 0x15E2 + +static inline u32 rn_readl(void __iomem *base_addr) +{ + return readl(base_addr - ACP_PHY_BASE_ADDRESS); +} + +static inline void rn_writel(u32 val, void __iomem *base_addr) +{ + writel(val, base_addr - ACP_PHY_BASE_ADDRESS); +}