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Wed, 05 Aug 2020 02:10:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 05 Aug 2020 02:11:43 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 05 Aug 2020 02:11:43 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 5 Aug 2020 09:11:42 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 5 Aug 2020 09:11:42 +0000 Received: from mkumard.nvidia.com (Not Verified[10.24.34.162]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 05 Aug 2020 02:11:41 -0700 From: Mohan Kumar To: , Subject: [PATCH 3/3] ALSA: hda/tegra: Add 100us dma stop delay Date: Wed, 5 Aug 2020 14:41:16 +0530 Message-ID: <20200805091116.2314-4-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200805091116.2314-1-mkumard@nvidia.com> References: <20200805091116.2314-1-mkumard@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596618653; bh=uZF+fL32kiXr/FFhU7XFb0VNeNdMUglasynYmIpWkSs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=SCUCtsZj/zyCN0eJx6ccBmjzvkvz51vk6bicoRkWPk7y0gCB85QxgDU2s33Qtdir1 Q4wM/ECwEXRm4PlKMf4L786Lo3EJ7jdF44Fl3GySa2q+o/Xv5uRoJriXx5CBWjW9y2 pVq9zFmrWlAWa4bsV+TjnJ5gKgI3WkGq19mGBY0iIju9KBvjI/8BfyuyTQbPxcBXXQ m7cVVoUuLjnE9srwBfDtCoqH4VQomMe2a1wogiB6cvKyeA+KTmPUUVi03gxXEMjDA1 ViS12XznCyn9ew+g6/O5gUpueQDBdL4EBcidQqyIVCwrNUeCPysOZ0QvGuAO83Zkjt Mq/ET4Dd0OVWA== Cc: alsa-devel@alsa-project.org, spujar@nvidia.com, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, treding@nvidia.com, Mohan Kumar X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Tegra HDA has audio data buffer for upto tens of frames, this buffer can help to avoid underflow. HW will keep issuing new data fetch request when buffers are not full and current BDL is not done. When SW disable DMA RUN bit for a stream, HW can't cancel the already issued data fetch request and hence it can't stop DMA. HW has to wait for all issued data fetch request get data returned before it stops DMA. This HW behavior is not in sync with HDA spec which says DMA RUN bit should be cleared within 1 audio frame. For Tegra, DMA RUN bit was active for more than one audio frame, due to this the timeout in snd_hdac_stream_sync function is not helping. When Stream reset set and clear happens during DMA RUN bit active state it results in Memory Decode error. Unfortunately, there is no way to detect when these data accesses have completed, but testing has shown that a 100us delay between Stream reset set and clear operation for Tegra avoids the memory decode error. Therefore, adding a 100us dma stop delay. Signed-off-by: Mohan Kumar --- sound/pci/hda/hda_tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index ecf98eb9df36..c94553bcca88 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -308,6 +308,7 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) return err; } bus->irq = irq_id; + bus->dma_stop_delay = 100; card->sync_irq = bus->irq; /*