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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=oss.nxp.com; Received: from VI1PR04MB5151.eurprd04.prod.outlook.com (2603:10a6:803:61::28) by VI1PR0401MB2654.eurprd04.prod.outlook.com (2603:10a6:800:58::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.21; Fri, 3 Sep 2021 14:53:57 +0000 Received: from VI1PR04MB5151.eurprd04.prod.outlook.com ([fe80::499b:ba92:db2e:3f28]) by VI1PR04MB5151.eurprd04.prod.outlook.com ([fe80::499b:ba92:db2e:3f28%7]) with mapi id 15.20.4457.026; Fri, 3 Sep 2021 14:53:57 +0000 From: Daniel Baluta To: broonie@kernel.org, pierre-louis.bossart@linux.intel.com, lgirdwood@gmail.com, robh+dt@kernel.org, ranjani.sridharan@linux.intel.com, kai.vehmanen@linux.intel.com Subject: [PATCH v2 2/2] dt-bindings: dsp: fsl: Add DSP optional clocks documentation Date: Fri, 3 Sep 2021 17:53:40 +0300 Message-Id: <20210903145340.225511-3-daniel.baluta@oss.nxp.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210903145340.225511-1-daniel.baluta@oss.nxp.com> References: <20210903145340.225511-1-daniel.baluta@oss.nxp.com> X-ClientProxiedBy: VI1PR07CA0200.eurprd07.prod.outlook.com (2603:10a6:802:3f::24) To VI1PR04MB5151.eurprd04.prod.outlook.com (2603:10a6:803:61::28) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (2a02:2f08:5708:8600:fd8d:b9e7:97b5:dd4a) by VI1PR07CA0200.eurprd07.prod.outlook.com (2603:10a6:802:3f::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.4 via Frontend Transport; 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By design we choose to manage DAI/DMA clocks from the kernel side because of the architecture of some i.MX8 boards. Clocks are handled by a special M4 core which runs a special firmware called SCFW (System Controler firmware). This communicates with A cores running Linux via a special Messaging Unit and implements a custom API which is already implemented by the Linux kernel i.MX clocks implementation. Note that these clocks are optional. We can use the DSP without them. Signed-off-by: Daniel Baluta --- .../devicetree/bindings/dsp/fsl,dsp.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml index 7afc9f2be13a..1453668c0194 100644 --- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -24,16 +24,49 @@ properties: maxItems: 1 clocks: + minItems: 3 items: - description: ipg clock - description: ocram clock - description: core clock + - description: esai0 core clock for accessing registers + - description: esai0 baud clock + - description: esai0 system clock + - description: esai0 spba clock required when ESAI is placed in slave mode + - description: SAI1 bus clock + - description: SAI1 master clock 0 + - description: SAI1 master clock 1 + - description: SAI1 master clock 2 + - description: SAI1 master clock 3 + - description: SAI3 bus clock + - description: SAI3 master clock 0 + - description: SAI3 master clock 1 + - description: SAI3 master clock 2 + - description: SAI3 master clock 3 + - description: SDMA3 root clock used for accessing registers + clock-names: + minItems: 3 items: - const: ipg - const: ocram - const: core + - const: esai0_core + - const: esai0_extal + - const: esai0_fsys + - const: esai0_spba + - const: sai1_bus + - const: sai1_mclk0 + - const: sai1_mclk1 + - const: sai1_mclk2 + - const: sai1_mclk3 + - const: sai3_bus + - const: sai3_mclk0 + - const: sai3_mclk1 + - const: sai3_mclk2 + - const: sai3_mclk3 + - const: smda3_root power-domains: description: