| Message ID | 20220111081518.982437-1-s.hauer@pengutronix.de (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | eba0f007751986ee401f2a1bcbdd3bdc845cb606 |
| Headers | show |
| Series | ASoC: fsl_sai: Enable combine mode soft | expand |
Hi Nicolin, Xiubo, Any input to this one? Sascha On Tue, Jan 11, 2022 at 09:15:18AM +0100, Sascha Hauer wrote: > The fsl_sai driver calculates the number of pins used and enables > multiple channels if necessary. This means the SAI expects data in > one FIFO per pin. The SDMA engine only services a single FIFO, so > multi pin support doesn't work at all. > > This patch enables the software combine mode in chips that support > it. With this the SAI presents only a single FIFO to the outside > and distributes the data into the different FIFOs internally. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > sound/soc/fsl/fsl_sai.c | 9 +++++++++ > sound/soc/fsl/fsl_sai.h | 1 + > 2 files changed, 10 insertions(+) > > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c > index 10544fa27dc0..cab015d96889 100644 > --- a/sound/soc/fsl/fsl_sai.c > +++ b/sound/soc/fsl/fsl_sai.c > @@ -517,6 +517,10 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, > FSL_SAI_CR5_FBT_MASK, val_cr5); > } > > + if (sai->soc_data->pins > 1) > + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), > + FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); > + > regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), > FSL_SAI_CR3_TRCE_MASK, > FSL_SAI_CR3_TRCE((1 << pins) - 1)); > @@ -1195,6 +1199,7 @@ static const struct fsl_sai_soc_data fsl_sai_vf610_data = { > .use_imx_pcm = false, > .use_edma = false, > .fifo_depth = 32, > + .pins = 1, > .reg_offset = 0, > .mclk0_is_mclk1 = false, > .flags = 0, > @@ -1204,6 +1209,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { > .use_imx_pcm = true, > .use_edma = false, > .fifo_depth = 32, > + .pins = 1, > .reg_offset = 0, > .mclk0_is_mclk1 = true, > .flags = 0, > @@ -1213,6 +1219,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { > .use_imx_pcm = true, > .use_edma = false, > .fifo_depth = 16, > + .pins = 2, > .reg_offset = 8, > .mclk0_is_mclk1 = false, > .flags = PMQOS_CPU_LATENCY, > @@ -1222,6 +1229,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { > .use_imx_pcm = true, > .use_edma = false, > .fifo_depth = 128, > + .pins = 8, > .reg_offset = 8, > .mclk0_is_mclk1 = false, > .flags = 0, > @@ -1231,6 +1239,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { > .use_imx_pcm = true, > .use_edma = true, > .fifo_depth = 64, > + .pins = 1, > .reg_offset = 0, > .mclk0_is_mclk1 = false, > .flags = 0, > diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h > index 9aaf231bc024..410f6e6a9137 100644 > --- a/sound/soc/fsl/fsl_sai.h > +++ b/sound/soc/fsl/fsl_sai.h > @@ -223,6 +223,7 @@ struct fsl_sai_soc_data { > bool use_edma; > bool mclk0_is_mclk1; > unsigned int fifo_depth; > + unsigned int pins; > unsigned int reg_offset; > unsigned int flags; > }; > -- > 2.30.2 > >
On Tue, 11 Jan 2022 09:15:18 +0100, Sascha Hauer wrote: > The fsl_sai driver calculates the number of pins used and enables > multiple channels if necessary. This means the SAI expects data in > one FIFO per pin. The SDMA engine only services a single FIFO, so > multi pin support doesn't work at all. > > This patch enables the software combine mode in chips that support > it. With this the SAI presents only a single FIFO to the outside > and distributes the data into the different FIFOs internally. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/1] ASoC: fsl_sai: Enable combine mode soft commit: eba0f007751986ee401f2a1bcbdd3bdc845cb606 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 10544fa27dc0..cab015d96889 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -517,6 +517,10 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, FSL_SAI_CR5_FBT_MASK, val_cr5); } + if (sai->soc_data->pins > 1) + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), + FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), FSL_SAI_CR3_TRCE_MASK, FSL_SAI_CR3_TRCE((1 << pins) - 1)); @@ -1195,6 +1199,7 @@ static const struct fsl_sai_soc_data fsl_sai_vf610_data = { .use_imx_pcm = false, .use_edma = false, .fifo_depth = 32, + .pins = 1, .reg_offset = 0, .mclk0_is_mclk1 = false, .flags = 0, @@ -1204,6 +1209,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { .use_imx_pcm = true, .use_edma = false, .fifo_depth = 32, + .pins = 1, .reg_offset = 0, .mclk0_is_mclk1 = true, .flags = 0, @@ -1213,6 +1219,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { .use_imx_pcm = true, .use_edma = false, .fifo_depth = 16, + .pins = 2, .reg_offset = 8, .mclk0_is_mclk1 = false, .flags = PMQOS_CPU_LATENCY, @@ -1222,6 +1229,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { .use_imx_pcm = true, .use_edma = false, .fifo_depth = 128, + .pins = 8, .reg_offset = 8, .mclk0_is_mclk1 = false, .flags = 0, @@ -1231,6 +1239,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { .use_imx_pcm = true, .use_edma = true, .fifo_depth = 64, + .pins = 1, .reg_offset = 0, .mclk0_is_mclk1 = false, .flags = 0, diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 9aaf231bc024..410f6e6a9137 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -223,6 +223,7 @@ struct fsl_sai_soc_data { bool use_edma; bool mclk0_is_mclk1; unsigned int fifo_depth; + unsigned int pins; unsigned int reg_offset; unsigned int flags; };
The fsl_sai driver calculates the number of pins used and enables multiple channels if necessary. This means the SAI expects data in one FIFO per pin. The SDMA engine only services a single FIFO, so multi pin support doesn't work at all. This patch enables the software combine mode in chips that support it. With this the SAI presents only a single FIFO to the outside and distributes the data into the different FIFOs internally. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- sound/soc/fsl/fsl_sai.c | 9 +++++++++ sound/soc/fsl/fsl_sai.h | 1 + 2 files changed, 10 insertions(+)