| Message ID | 20220210065057.13555-5-mkumard@nvidia.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Tegra234 HDA support | expand |
On 2/10/22 08:50, Mohan Kumar wrote: > Add hda clocks, memory ,power and reset binding entries > for Tegra234. > > Signed-off-by: Mohan Kumar <mkumard@nvidia.com> > --- > include/dt-bindings/clock/tegra234-clock.h | 4 ++++ > include/dt-bindings/memory/tegra234-mc.h | 6 ++++++ > include/dt-bindings/power/tegra234-powergate.h | 9 +++++++++ > include/dt-bindings/reset/tegra234-reset.h | 2 ++ > 4 files changed, 21 insertions(+) > create mode 100644 include/dt-bindings/power/tegra234-powergate.h > > diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h > index 8d7e66e1b6ef..c014269b7245 100644 > --- a/include/dt-bindings/clock/tegra234-clock.h > +++ b/include/dt-bindings/clock/tegra234-clock.h > @@ -30,5 +30,9 @@ > #define TEGRA234_CLK_PLLC4 237U > /** @brief 32K input clock provided by PMIC */ > #define TEGRA234_CLK_CLK_32K 289U > +/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ > +#define TEGRA234_CLK_AZA_2XBIT 457U > +/** @brief aza_2xbitclk / 2 (aza_bitclk) */ > +#define TEGRA234_CLK_AZA_BIT 458U > > #endif > diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h > index 2662f70c15c6..f538fc442cee 100644 > --- a/include/dt-bindings/memory/tegra234-mc.h > +++ b/include/dt-bindings/memory/tegra234-mc.h > @@ -7,6 +7,8 @@ > #define TEGRA234_SID_INVALID 0x00 > #define TEGRA234_SID_PASSTHROUGH 0x7f > > +/* NISO0 SMMU STREAM IDs */ > +#define TEGRA234_SID_NISO0_HDA 0x03 Please follow the existing convention in this file. /* NISO0 stream IDs */ #define TEGRA234_SID_HDA 0x03 > > /* NISO1 stream IDs */ > #define TEGRA234_SID_SDMMC4 0x02 > @@ -16,6 +18,10 @@ > * memory client IDs > */ > > +/* High-definition audio (HDA) read clients */ > +#define TEGRA234_MEMORY_CLIENT_HDAR 0x15 > +/* High-definition audio (HDA) write clients */ > +#define TEGRA234_MEMORY_CLIENT_HDAW 0x35 > /* sdmmcd memory read client */ > #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 > /* sdmmcd memory write client */ > diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h > new file mode 100644 > index 000000000000..3c5575a51296 > --- /dev/null > +++ b/include/dt-bindings/power/tegra234-powergate.h > @@ -0,0 +1,9 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. */ > + > +#ifndef __ABI_MACH_T234_POWERGATE_T234_H_ > +#define __ABI_MACH_T234_POWERGATE_T234_H_ > + > +#define TEGRA234_POWER_DOMAIN_DISP 3U > + > +#endif > diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h > index 50e13bced642..2ab61c69a3d9 100644 > --- a/include/dt-bindings/reset/tegra234-reset.h > +++ b/include/dt-bindings/reset/tegra234-reset.h > @@ -10,6 +10,8 @@ > * @brief Identifiers for Resets controllable by firmware > * @{ > */ > +#define TEGRA234_RESET_HDA 20U > +#define TEGRA234_RESET_HDACODEC 21U > #define TEGRA234_RESET_SDMMC4 85U > #define TEGRA234_RESET_UARTA 100U >
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8d7e66e1b6ef..c014269b7245 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -30,5 +30,9 @@ #define TEGRA234_CLK_PLLC4 237U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ +#define TEGRA234_CLK_AZA_2XBIT 457U +/** @brief aza_2xbitclk / 2 (aza_bitclk) */ +#define TEGRA234_CLK_AZA_BIT 458U #endif diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 2662f70c15c6..f538fc442cee 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -7,6 +7,8 @@ #define TEGRA234_SID_INVALID 0x00 #define TEGRA234_SID_PASSTHROUGH 0x7f +/* NISO0 SMMU STREAM IDs */ +#define TEGRA234_SID_NISO0_HDA 0x03 /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 @@ -16,6 +18,10 @@ * memory client IDs */ +/* High-definition audio (HDA) read clients */ +#define TEGRA234_MEMORY_CLIENT_HDAR 0x15 +/* High-definition audio (HDA) write clients */ +#define TEGRA234_MEMORY_CLIENT_HDAW 0x35 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 /* sdmmcd memory write client */ diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h new file mode 100644 index 000000000000..3c5575a51296 --- /dev/null +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T234_POWERGATE_T234_H_ +#define __ABI_MACH_T234_POWERGATE_T234_H_ + +#define TEGRA234_POWER_DOMAIN_DISP 3U + +#endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 50e13bced642..2ab61c69a3d9 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -10,6 +10,8 @@ * @brief Identifiers for Resets controllable by firmware * @{ */ +#define TEGRA234_RESET_HDA 20U +#define TEGRA234_RESET_HDACODEC 21U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U
Add hda clocks, memory ,power and reset binding entries for Tegra234. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> --- include/dt-bindings/clock/tegra234-clock.h | 4 ++++ include/dt-bindings/memory/tegra234-mc.h | 6 ++++++ include/dt-bindings/power/tegra234-powergate.h | 9 +++++++++ include/dt-bindings/reset/tegra234-reset.h | 2 ++ 4 files changed, 21 insertions(+) create mode 100644 include/dt-bindings/power/tegra234-powergate.h