From patchwork Thu Apr 14 16:22:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12813714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30701C433F5 for ; Thu, 14 Apr 2022 16:29:37 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 751B118B3; Thu, 14 Apr 2022 18:28:45 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 751B118B3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1649953775; bh=O0S5Hnj9KiEz4pA9LRQVFNY4urthCBVOtRXT8VUS2tE=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=YSZFU5jY82M3SZs5vPa0/qr76O7TWWzKriNnNWtG7qQPab3YS/ndF4VJuQNFjXTxv bU0dfKWq/XY6Gneti+CiNieRklCze4Rkh0aHusVPO/HTv+10wLDSvV4PkAgJgWsdwL GSnTKL78MiLiSlFeT/aH4ij0F0fhHjGLX0mOIWwk= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 253C1F805C5; Thu, 14 Apr 2022 18:23:35 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id E3B94F8056F; Thu, 14 Apr 2022 18:23:27 +0200 (CEST) Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 998BCF80526 for ; Thu, 14 Apr 2022 18:22:58 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 998BCF80526 Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nf2FE-0007R3-Qp; Thu, 14 Apr 2022 18:22:56 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1nf2FD-00313A-VF; Thu, 14 Apr 2022 18:22:54 +0200 Received: from sha by dude02.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nf2F9-00GuCF-Kg; Thu, 14 Apr 2022 18:22:51 +0200 From: Sascha Hauer To: alsa-devel@alsa-project.org Subject: [PATCH v6 15/21] ASoC: fsl_micfil: simplify clock setting Date: Thu, 14 Apr 2022 18:22:43 +0200 Message-Id: <20220414162249.3934543-16-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220414162249.3934543-1-s.hauer@pengutronix.de> References: <20220414162249.3934543-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: alsa-devel@alsa-project.org Cc: Xiubo Li , Fabio Estevam , Sascha Hauer , Vinod Koul , Mark Brown , NXP Linux Team , kernel@pengutronix.de, dmaengine@vger.kernel.org, Shengjiu Wang X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The reference manual has this for calculating the micfil internal clock divider: MICFIL Clock rate clkdiv = ----------------- 8 * OSR * outrate (with OSR == Oversampling Rate, outrate == output sample rate) The driver first sets the MICFIL Clock rate to (outrate * 1024) and then calculates back the clkdiv value from the above calculation. Simplify this by using a fixed clkdiv value of 8 and set the MICFIL Clock rate to (outrate * clkdiv * OSR * 8). While at it drop disabling the clock before setting its rate. The MICFIL module is disabled when the rate is changed and it is also resetted before it is started again, so I doubt it's necessary to disable the clock. Signed-off-by: Sascha Hauer Acked-by: Shengjiu Wang --- Notes: Changes since v3: - Don't use uninitialized and no longer present struct fsl_micfil::osr sound/soc/fsl/fsl_micfil.c | 45 ++++---------------------------------- 1 file changed, 4 insertions(+), 41 deletions(-) diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c index 3ddc988b4fe65..4d8dfb2c22290 100644 --- a/sound/soc/fsl/fsl_micfil.c +++ b/sound/soc/fsl/fsl_micfil.c @@ -110,19 +110,6 @@ static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { snd_soc_get_enum_double, snd_soc_put_enum_double), }; -static inline int get_clk_div(struct fsl_micfil *micfil, - unsigned int rate) -{ - long mclk_rate; - int clk_div; - - mclk_rate = clk_get_rate(micfil->mclk); - - clk_div = mclk_rate / (rate * MICFIL_OSR_DEFAULT * 8); - - return clk_div; -} - /* The SRES is a self-negated bit which provides the CPU with the * capability to initialize the PDM Interface module through the * slave-bus interface. This bit always reads as zero, and this @@ -146,24 +133,6 @@ static int fsl_micfil_reset(struct device *dev) return 0; } -static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil, - unsigned int freq) -{ - struct device *dev = &micfil->pdev->dev; - int ret; - - clk_disable_unprepare(micfil->mclk); - - ret = clk_set_rate(micfil->mclk, freq * 1024); - if (ret) - dev_warn(dev, "failed to set rate (%u): %d\n", - freq * 1024, ret); - - clk_prepare_enable(micfil->mclk); - - return ret; -} - static int fsl_micfil_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { @@ -237,13 +206,12 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, static int fsl_set_clock_params(struct device *dev, unsigned int rate) { struct fsl_micfil *micfil = dev_get_drvdata(dev); - int clk_div; + int clk_div = 8; int ret; - ret = fsl_micfil_set_mclk_rate(micfil, rate); - if (ret < 0) - dev_err(dev, "failed to set mclk[%lu] to rate %u\n", - clk_get_rate(micfil->mclk), rate); + ret = clk_set_rate(micfil->mclk, rate * clk_div * MICFIL_OSR_DEFAULT * 8); + if (ret) + return ret; /* set CICOSR */ ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, @@ -252,11 +220,6 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate) if (ret) return ret; - /* set CLK_DIV */ - clk_div = get_clk_div(micfil, rate); - if (clk_div < 0) - ret = -EINVAL; - ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, MICFIL_CTRL2_CLKDIV, FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));