From patchwork Wed Jul 6 21:13:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12908636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EC42C43334 for ; Wed, 6 Jul 2022 21:15:16 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id D71A716B1; Wed, 6 Jul 2022 23:14:24 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz D71A716B1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1657142114; bh=y43SJFn3QG35mcbrsANW2b9HcvspbkQEj8Jr+25Hw54=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=P4H2RzB5V/pxRQrC3/lMGOGjvs/VDcB2e6qik0qM3EXzcXSWjT3CWK5srMI/RXrrR PfrlbBZmwYZM+gkbFm4zMqI7IfqbXsHdqF9giB50pJfOPQy8tN5a7XnSrT+u2dMgK4 C8xV7gCgm702OIpXoOhv8dWoHK8XkvvRFjAX+brM= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id B71F5F8053D; Wed, 6 Jul 2022 23:12:56 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 1F777F80551; Wed, 6 Jul 2022 23:12:55 +0200 (CEST) Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 2CDBDF80551 for ; Wed, 6 Jul 2022 23:12:51 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 2CDBDF80551 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ng1EmV1A" Received: by mail-ed1-x531.google.com with SMTP id n8so20845786eda.0 for ; Wed, 06 Jul 2022 14:12:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iCuO3VFv3rm5+5Ss/MNF7iJIR1x3LJAwtPwGLPWckEU=; b=ng1EmV1Axl1NLL1g+HJ8HMlNj2yF38LfwGe9b6HXRvt8xye1dkzsWrGPLhc5o9dFQu aDdgXkvTfoas3OIjMWLKqUx0A1zX6VL2E9UjrlxHsH+IfI/EkU4fv9TEjGch4oslXZ0+ FP6//5dvPQ6s5ISf7P7gCNQTaEjmQZ5ue3y06fcZQtoMDaxvPL3zP6lSdza8p2heLokJ 4V0YfWcPCRIPDd0Ch69k4pmQq0LepPjWR9s6EFahXptEpD/BNy1gBEg+gpvzDK96uw7g e0WXbaLtX2rW50Jo8Z9tGgQ1qnkKRhfE1TZrmKygHNEOApGsZ4ZYSGNHzoiPbjrG4G56 1lJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iCuO3VFv3rm5+5Ss/MNF7iJIR1x3LJAwtPwGLPWckEU=; b=Ey8HptU/zZuo8W2qZ0Fp5VWwrOj3FpxGOjRp9tBSEkLXVTSBuaGvjV6lBlRQJGYoNB XvLPsM6FrhFgruzbZOCF5T4ko4vM5JfwgBr6byxTWGkiWrqD2T59nOYrb1aGwJhD43Y4 aiY/PwSrflcLh2t2FW5RJTn6MUeYtgBcQgUlguR9G9vxwGKVHDctrPSBHtZfJyaoxr5z ygxAN19yMuL+FJaI+0BJ+5fDHbvcaNVZ8gMR85up6jA8klqPmgs5B9DW9TsPERZLAy+c +S/8u5XGOitv46oF8qDB3wdjPTzpw+rEAv3XuuO6HG4Hi6+cD3ZOJJRiC6IeQb47pYmg rRGQ== X-Gm-Message-State: AJIora+xaUPuGiYMg5doPpJtNtOM9jX86YOX0DeuBdP8qPqUYZLeVWqA ECFKVNnLNzpsJV3NDbBhBe0= X-Google-Smtp-Source: AGRyM1uVRMejVGpTyJ0e1CDHYsj+AxD0TLlzxv5mmjWtzauLAobFyIg0Ey/l2Fwx9ajYCodB3lAnRw== X-Received: by 2002:aa7:c9cf:0:b0:435:de3b:c499 with SMTP id i15-20020aa7c9cf000000b00435de3bc499mr55992284edt.321.1657141970441; Wed, 06 Jul 2022 14:12:50 -0700 (PDT) Received: from localhost (92.40.202.8.threembb.co.uk. [92.40.202.8]) by smtp.gmail.com with ESMTPSA id a18-20020a50ff12000000b0043789187c1esm21344346edu.80.2022.07.06.14.12.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:12:49 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Subject: [PATCH 08/11] ASoC: jz4740-i2s: Align macro values and sort includes Date: Wed, 6 Jul 2022 22:13:27 +0100 Message-Id: <20220706211330.120198-9-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220706211330.120198-1-aidanmacdonald.0x0@gmail.com> References: <20220706211330.120198-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Some purely cosmetic changes: line up all the macro values to make things easier to read and sort the includes alphabetically. Signed-off-by: Aidan MacDonald Acked-by: Paul Cercueil --- sound/soc/jz4740/jz4740-i2s.c | 66 +++++++++++++++++------------------ 1 file changed, 32 insertions(+), 34 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index b8d2723c5f90..3a21ee9d34d1 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -4,6 +4,9 @@ */ #include +#include +#include +#include #include #include #include @@ -13,11 +16,6 @@ #include #include -#include -#include - -#include - #include #include #include @@ -35,36 +33,36 @@ #define JZ_REG_AIC_CLK_DIV 0x30 #define JZ_REG_AIC_FIFO 0x34 -#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) -#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) -#define JZ_AIC_CONF_I2S BIT(4) -#define JZ_AIC_CONF_RESET BIT(3) -#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) -#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) -#define JZ_AIC_CONF_ENABLE BIT(0) - -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) -#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) -#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) -#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) -#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) -#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) +#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) +#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) +#define JZ_AIC_CONF_I2S BIT(4) +#define JZ_AIC_CONF_RESET BIT(3) +#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) +#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) +#define JZ_AIC_CONF_ENABLE BIT(0) + +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) +#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) +#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) +#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) +#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) +#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) #define JZ_AIC_CTRL_FLUSH BIT(8) -#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) -#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) -#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) -#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) -#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) -#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) -#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) - -#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) -#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) -#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) -#define JZ_AIC_I2S_FMT_MSB BIT(0) - -#define JZ_AIC_I2S_STATUS_BUSY BIT(2) +#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) +#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) +#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) +#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) +#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) +#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) +#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) + +#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) +#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) +#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) +#define JZ_AIC_I2S_FMT_MSB BIT(0) + +#define JZ_AIC_I2S_STATUS_BUSY BIT(2) struct i2s_soc_info { struct snd_soc_dai_driver *dai;