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Tue, 15 Nov 2022 01:19:53 -0600 From: V sujith kumar Reddy To: , Subject: [PATCH 2/4] ASoC: SOF: amd: Fix for selecting clock source as external clock. Date: Tue, 15 Nov 2022 12:49:54 +0530 Message-ID: <20221115072001.1931617-2-Vsujithkumar.Reddy@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221115072001.1931617-1-Vsujithkumar.Reddy@amd.com> References: <20221115072001.1931617-1-Vsujithkumar.Reddy@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000EE3E:EE_|SJ1PR12MB6266:EE_ X-MS-Office365-Filtering-Correlation-Id: 15bd6ff4-12fc-4a1e-32e9-08dac6d9e2dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: v08EEO4kHVKEXndxD3FeTwyFW8puM1jt4NQQQ+NDPItEkrbTLwndMsPzqIArCUFfRXaJjSJGT6UhWdLyi0QeSD4ta079LiOlaeh00tb3acUPbORBZx2M0+0xUMeRw3MDjNqoUDbDKr4ZFOvjBx3IVzdtj2EbE7AV1VxDNLWe/5zYExH3fGFFe8SUBpc5BGArXkCcC3MeKsWFLxF6+QMPgDIETVWPlGSYkkZXXU3tKN5zqGOVYHJD8idEcUQAAUVfFFu/+XX96/zp5xcF3FuW28pJiTaVQG/GN279cP8sqxB/PHpIEK+ccKP6ovkTAGUs/TAKa59XDPmowWsysCw+6poBA8VGTV0H1NHsZRUvlUIxT3uYhQS/4d7WbP6Tgm2eU6FIFeg4oRf3ys9sUdfzokHZq8vlE30E0irw9B4Jd1J0FpUTJrdNSIHZlpAjjPfsgV53IEuMyOxItIsZadb8a5CUAeVEQxKZWkLwInpZNygnSm5EZSg9GcqdBWdZiWxgqVt7zfMFc874wMrCSRRqQ4lheLyYrENhqZ/l/4HdPFj6Q9n9p3Xgok7vw5qSB6w5pThYCG19BtlZq9jDxPrc5Bp1UuATS6NYRCdiL94QtnVl1gd+Ta4Q95+S1BiH2ML++k3M/s+8MEL2LohiOy6fBNdY/B85E3xnS73peVb54jcAlUOo24ldoVXRI21QAPB4iOMu2btBkL1Dv1vhItiVlZv6t3wvBITCAYSPuVNRVK9RxN00rdkjOC4rTeNJz3S8BleJmQbEDjXlxjLxww+Q++rIIWCzqennfUj8wFYVS3rVg0crwlNSdllsJd+frypd X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(396003)(376002)(346002)(39860400002)(136003)(451199015)(46966006)(36840700001)(40470700004)(82310400005)(40460700003)(36756003)(40480700001)(86362001)(83380400001)(26005)(7696005)(1076003)(2616005)(47076005)(426003)(336012)(186003)(82740400003)(356005)(81166007)(36860700001)(7416002)(8936002)(4326008)(8676002)(5660300002)(41300700001)(2906002)(70206006)(478600001)(70586007)(316002)(54906003)(110136005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2022 07:20:34.2162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15bd6ff4-12fc-4a1e-32e9-08dac6d9e2dc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6266 Cc: Daniel Baluta , Jiapeng Chong , Sunil-kumar.Dommati@amd.com, ssabakar@amd.com, Kai Vehmanen , venkataprasad.potturu@amd.com, Bard Liao , Basavaraj.Hiregoudar@amd.com, Takashi Iwai , Pierre-Louis Bossart , Liam Girdwood , Ranjani Sridharan , Vijendar.Mukunda@amd.com, V sujith kumar Reddy , Peter Ujfalusi , Ajit Kumar Pandey , open list , "moderated list:SOUND - SOUND OPEN FIRMWARE \(SOF\) DRIVERS" X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" By default clock source is selected as internal clock of 96Mhz which is not configurable. Now we select the clock source to external clock (ACLK) which can be configurable to different clock ranges depending on usecase. Signed-off-by: V sujith kumar Reddy --- sound/soc/sof/amd/acp.c | 4 +++- sound/soc/sof/amd/acp.h | 8 ++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index 36966643e36a..47115a77c92c 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -390,6 +390,7 @@ static int acp_power_on(struct snd_sof_dev *sdev) static int acp_reset(struct snd_sof_dev *sdev) { + const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); unsigned int val; int ret; @@ -410,6 +411,7 @@ static int acp_reset(struct snd_sof_dev *sdev) if (ret < 0) dev_err(sdev->dev, "timeout in releasing reset\n"); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); return ret; } @@ -456,7 +458,7 @@ int amd_sof_acp_resume(struct snd_sof_dev *sdev) return ret; } - snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, 0x03); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); ret = acp_memory_init(sdev); diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index 1529c6d9bf9b..76ad963faec1 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -69,6 +69,14 @@ #define BOX_SIZE_512 0x200 #define BOX_SIZE_1024 0x400 +enum clock_source { + ACP_CLOCK_96M = 0, + ACP_CLOCK_48M, + ACP_CLOCK_24M, + ACP_CLOCK_ACLK, + ACP_CLOCK_MCLK, +}; + struct acp_atu_grp_pte { u32 low; u32 high;