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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id h15-20020a1709062dcf00b008dffda52d71sm7051880eji.124.2023.03.07.23.35.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 23:35:31 -0800 (PST) From: Svyatoslav Ryhel To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Thierry Reding , Jonathan Hunter , Jaroslav Kysela , Takashi Iwai , Svyatoslav Ryhel , Maxim Schwalm , Dmitry Osipenko Subject: [PATCH v2 7/8] dt-bindings: sound: nvidia,tegra-audio: add MAX9808x CODEC Date: Wed, 8 Mar 2023 09:35:01 +0200 Message-Id: <20230308073502.5421-8-clamor95@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230308073502.5421-1-clamor95@gmail.com> References: <20230308073502.5421-1-clamor95@gmail.com> MIME-Version: 1.0 X-MailFrom: clamor95@gmail.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: TPYVVOUWJSJOTORRDSMYA5ZCKSIWFMEG X-Message-ID-Hash: TPYVVOUWJSJOTORRDSMYA5ZCKSIWFMEG X-Mailman-Approved-At: Wed, 08 Mar 2023 11:20:25 +0000 CC: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, linux-tegra@vger.kernel.org, linux-staging@lists.linux.dev X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Add dt-binding for MAX9808x CODEC. Signed-off-by: Svyatoslav Ryhel --- .../sound/nvidia,tegra-audio-max9808x.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max9808x.yaml diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max9808x.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max9808x.yaml new file mode 100644 index 000000000000..fc89dbd6bf24 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max9808x.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-max9808x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra audio complex with MAX9808x CODEC + +maintainers: + - Jon Hunter + - Thierry Reding + +allOf: + - $ref: nvidia,tegra-audio-common.yaml# + +properties: + compatible: + oneOf: + - items: + - pattern: '^[a-z0-9]+,tegra-audio-max98088(-[a-z0-9]+)+$' + - const: nvidia,tegra-audio-max98088 + - items: + - pattern: '^[a-z0-9]+,tegra-audio-max98089(-[a-z0-9]+)+$' + - const: nvidia,tegra-audio-max98089 + + nvidia,audio-routing: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: | + A list of the connections between audio components. + Each entry is a pair of strings, the first being the connection's sink, + the second being the connection's source. Valid names for sources and + sinks are the pins (documented in the binding document), + and the jacks on the board. + minItems: 2 + items: + enum: + # Board Connectors + - "Int Spk" + - "Headphone Jack" + - "Earpiece" + - "Headset Mic" + - "Internal Mic 1" + - "Internal Mic 2" + + # CODEC Pins + - HPL + - HPR + - SPKL + - SPKR + - RECL + - RECR + - INA1 + - INA2 + - INB1 + - INB2 + - MIC1 + - MIC2 + - MICBIAS + +unevaluatedProperties: false + +examples: + - | + #include + #include + sound { + compatible = "lge,tegra-audio-max98089-p895", + "nvidia,tegra-audio-max98089"; + nvidia,model = "LG Optimus Vu MAX98089"; + + nvidia,audio-routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Int Spk", "SPKL", + "Int Spk", "SPKR", + "Earpiece", "RECL", + "Earpiece", "RECR", + "INA1", "Headset Mic", + "MIC1", "MICBIAS", + "MICBIAS", "Internal Mic 1", + "MIC2", "Internal Mic 2"; + + nvidia,i2s-controller = <&tegra_i2s0>; + nvidia,audio-codec = <&codec>; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + };