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[1/8] ASoC: codecs: es8316: Add support for 24 MHz MCLK

Message ID 20230629112449.1755928-2-cezary.rojewski@intel.com (mailing list archive)
State Accepted
Commit be7dc10ab0bc247c2abbdefdaa9d5196df88e9d1
Headers show
Series ASoC: Intel: avs: New boards and fixes to existing ones | expand

Commit Message

Cezary Rojewski June 29, 2023, 11:24 a.m. UTC 
MCLK operates on 24MHz on Intel KabyLake-based platforms. To support
that frequency add new MCLK-LRCK ratio.

While at it, utilize ARRAY_SIZE rather than hardcode to improve
robustness.

Cc: Zhu Ning <zhuning@everest-semi.com>
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
---
 sound/soc/codecs/es8316.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c
index 34cf60769b62..5d1fd505d6ba 100644
--- a/sound/soc/codecs/es8316.c
+++ b/sound/soc/codecs/es8316.c
@@ -27,9 +27,9 @@ 
  * MCLK/LRCK ratios, but we also add ratio 400, which is commonly used on
  * Intel Cherry Trail platforms (19.2MHz MCLK, 48kHz LRCK).
  */
-#define NR_SUPPORTED_MCLK_LRCK_RATIOS 6
+#define NR_SUPPORTED_MCLK_LRCK_RATIOS ARRAY_SIZE(supported_mclk_lrck_ratios)
 static const unsigned int supported_mclk_lrck_ratios[] = {
-	256, 384, 400, 512, 768, 1024
+	256, 384, 400, 500, 512, 768, 1024
 };
 
 struct es8316_priv {