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Wed, 05 Jul 2023 19:28:34 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5EF6A100057; Wed, 5 Jul 2023 19:28:33 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 54E1524C42F; Wed, 5 Jul 2023 19:28:33 +0200 (CEST) Received: from localhost (10.201.21.121) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Wed, 5 Jul 2023 19:28:32 +0200 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH 03/10] dt-bindings: bus: add device tree bindings for ETZPC Date: Wed, 5 Jul 2023 19:27:52 +0200 Message-ID: <20230705172759.1610753-4-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230705172759.1610753-1-gatien.chevallier@foss.st.com> References: <20230705172759.1610753-1-gatien.chevallier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.121] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-05_09,2023-07-05_01,2023-05-22_02 Message-ID-Hash: SI6WMQ4KVARRVN2N4N5CQ3EKSHLF6W76 X-Message-ID-Hash: SI6WMQ4KVARRVN2N4N5CQ3EKSHLF6W76 X-MailFrom: prvs=5550e8e426=gatien.chevallier@foss.st.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Document ETZPC (Extended TrustZone protection controller). ETZPC is a firewall controller. Signed-off-by: Gatien Chevallier --- .../bindings/bus/st,stm32-etzpc.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml diff --git a/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml b/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml new file mode 100644 index 000000000000..327fb0b84c0b --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Extended TrustZone protection controller bindings + +description: | + The ETZPC configures TrustZone security in a SoC having bus masters and + devices with programmable-security attributes (securable resources). + +maintainers: + - Gatien Chevallier + +properties: + compatible: + const: "st,stm32-etzpc" + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + feature-domain-controller: true + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + properties: + feature-domains: + minItems: 1 + maxItems: 2 + description: + The first argument must always be a phandle that references to the + firewall controller of the peripheral. The second can contain the + platform specific firewall ID of the peripheral. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - feature-domain-controller + - "#feature-domain-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its domain + // controller. + // Access rights are verified before creating devices. + + #include + #include + #include + + etzpc: etzpc@5c007000 { + compatible = "st,stm32mp13-sys-bus"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + feature-domain-controller; + #feature-domain-cells = <1>; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 17>; + status = "disabled"; + }; + };