From patchwork Tue Jul 25 09:23:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 13326190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4AFBC001DF for ; Tue, 25 Jul 2023 09:29:23 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 2C6B4151B; Tue, 25 Jul 2023 11:28:32 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 2C6B4151B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1690277362; bh=iq4rNK6RR61clK9JWynQM9M41YZBhay5oStrLABXE6c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; b=KpNRHfbVELjPUQQJDBgIFl9vnZ9OI32WaoqzOlDp4bxdvQy933IVftuyWPh5OpGbP vbELbkdmuqXJOOcryta2+P/GCqsZ71pRXuE1RCj9I9Nk9DDEbnm7LOK6YvRILRgH1m pavoAsQet1jahJG51A8M7ZYvTYUk/8mm/5+pjowY= Received: by alsa1.perex.cz (Postfix, from userid 50401) id 97CC0F805E8; Tue, 25 Jul 2023 11:25:42 +0200 (CEST) Received: from mailman-core.alsa-project.org (mailman-core.alsa-project.org [10.254.200.10]) by alsa1.perex.cz (Postfix) with ESMTP id 208E2F805F8; Tue, 25 Jul 2023 11:25:42 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id DB525F805F1; Tue, 25 Jul 2023 11:25:35 +0200 (CEST) Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id CC865F805E8 for ; Tue, 25 Jul 2023 11:25:32 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz CC865F805E8 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key, unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256 header.s=gm1 header.b=c5NjOUYe Received: by mail.gandi.net (Postfix) with ESMTPA id 0E5D740019; Tue, 25 Jul 2023 09:25:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1690277132; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Qb9JJd2ccR7R8C3gjckd4+51tlc3N7Nrektp0ymXFJ4=; b=c5NjOUYes6dhntB5+RrrYjoonyWCtKHMZ0/HXvaURv6PJoFwfHyFRA3TUj24KR2cDehmBY nXkpGgWny5B62KtQBa1YkHf2Kz1rY2988A6OyA3ql6PMeSS3BclrFd8Qcg9VXJ1F5ZxS6A wbNvbyZutN+xLstAQeJAPnwCkMsnGJz3n6f4x8avIuJbnsrpmArVqBwYCPfkYRe+MpAEZw o0C6R6rjRzQuaNYwoKBS72GzOH0bG4G+mZvRqLemTrp+3LsZ/5zz1RSGWGOWNSeGP0iG8+ vMYhE/dLf84Fra35LwzfrNQvyUKuPCE7kPdrI+iTB4UPHe1jIJ6ZxM4OaEjaGQ== From: Herve Codina To: Herve Codina , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Linus Walleij , Qiang Zhao , Li Yang , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Christophe Leroy Cc: netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 13/26] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag Date: Tue, 25 Jul 2023 11:23:49 +0200 Message-ID: <20230725092417.43706-14-herve.codina@bootlin.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230725092417.43706-1-herve.codina@bootlin.com> References: <20230725092417.43706-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: herve.codina@bootlin.com Message-ID-Hash: XSASRLRBIEYNSYFWNVOT2XMUMKGSZSEL X-Message-ID-Hash: XSASRLRBIEYNSYFWNVOT2XMUMKGSZSEL X-MailFrom: herve.codina@bootlin.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: In order to support runtime timeslot route changes, some operations will be different according the routing table used (common Rx and Tx table or one table for Rx and one for Tx). The is_tsa_64rxtx flag is introduced to avoid extra computation to determine the table format each time we need it. It is set once at initialization. Signed-off-by: Herve Codina --- drivers/soc/fsl/qe/qmc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index d02acbc1d7e1..64c3bfc16010 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -216,6 +216,7 @@ struct qmc { u16 __iomem *int_curr; dma_addr_t int_dma_addr; size_t int_size; + bool is_tsa_64rxtx; struct list_head chan_head; struct qmc_chan *chans[64]; }; @@ -696,7 +697,7 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable) * Setup one common 64 entries table or two 32 entries (one for Tx * and one for Tx) according to assigned TS numbers. */ - if (info.nb_tx_ts > 32 || info.nb_rx_ts > 32) + if (chan->qmc->is_tsa_64rxtx) return qmc_chan_setup_tsa_64rxtx(chan, &info, enable); ret = qmc_chan_setup_tsa_32rx(chan, &info, enable); @@ -1053,6 +1054,7 @@ static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *in * Everything was previously checked, Tx and Rx related stuffs are * identical -> Used Rx related stuff to build the table */ + qmc->is_tsa_64rxtx = true; /* Invalidate all entries */ for (i = 0; i < 64; i++) @@ -1081,6 +1083,7 @@ static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial_info * Use a Tx 32 entries table and a Rx 32 entries table. * Everything was previously checked. */ + qmc->is_tsa_64rxtx = false; /* Invalidate all entries */ for (i = 0; i < 32; i++) {