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Tue, 25 Jul 2023 18:43:56 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1D06210002A; Tue, 25 Jul 2023 18:43:56 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0F5FA27FAB5; Tue, 25 Jul 2023 18:43:56 +0200 (CEST) Received: from localhost (10.201.21.121) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 25 Jul 2023 18:43:55 +0200 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v2 08/11] arm64: dts: st: add RIFSC as a domain controller for STM32MP25x boards Date: Tue, 25 Jul 2023 18:41:01 +0200 Message-ID: <20230725164104.273965-9-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230725164104.273965-1-gatien.chevallier@foss.st.com> References: <20230725164104.273965-1-gatien.chevallier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.121] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-25_08,2023-07-25_01,2023-05-22_02 Message-ID-Hash: G5VC6DG7BEVOCYIXX5LGCBS62IHA2WCP X-Message-ID-Hash: G5VC6DG7BEVOCYIXX5LGCBS62IHA2WCP X-MailFrom: prvs=557065b4ce=gatien.chevallier@foss.st.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: RIFSC is a firewall controller. Change its compatible so that is matches the documentation and reference RIFSC as a feature-domain-controller. Signed-off-by: Gatien Chevallier --- Changes in V2: - Fix rifsc node name - Move the "ranges" property under the "feature-domains" one arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5268a4321841..cb084381e4cd 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -105,11 +105,13 @@ soc@0 { interrupt-parent = <&intc>; ranges = <0x0 0x0 0x0 0x80000000>; - rifsc: rifsc-bus@42080000 { - compatible = "simple-bus"; + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc"; reg = <0x42080000 0x1000>; #address-cells = <1>; #size-cells = <1>; + feature-domain-controller; + #feature-domain-cells = <1>; ranges; usart2: serial@400e0000 { @@ -117,6 +119,7 @@ usart2: serial@400e0000 { reg = <0x400e0000 0x400>; interrupts = ; clocks = <&ck_flexgen_08>; + feature-domains = <&rifsc 32>; status = "disabled"; }; };