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Mon, 31 Jul 2023 11:57:33 -0500 (CDT) Received: from ediex01.ad.cirrus.com (198.61.84.80) by ediex01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 31 Jul 2023 17:57:30 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by ediex01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.2.1118.30 via Frontend Transport; Mon, 31 Jul 2023 17:57:30 +0100 Received: from EDIN4L06LR3.ad.cirrus.com (EDIN4L06LR3.ad.cirrus.com [198.61.64.107]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 55A3D45D; Mon, 31 Jul 2023 16:57:30 +0000 (UTC) From: Richard Fitzgerald To: CC: , , , , Richard Fitzgerald Subject: [PATCH 2/9] ALSA: hda/cs35l56: Do not mark cache dirty after REINIT Date: Mon, 31 Jul 2023 17:57:19 +0100 Message-ID: <20230731165726.7940-3-rf@opensource.cirrus.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230731165726.7940-1-rf@opensource.cirrus.com> References: <20230731165726.7940-1-rf@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-GUID: kFB1f_oNiNMpBEAsCAcGXST23BTvhCOS X-Proofpoint-ORIG-GUID: kFB1f_oNiNMpBEAsCAcGXST23BTvhCOS X-Proofpoint-Spam-Reason: safe Message-ID-Hash: HLVNFMRTQ2AB744M6FAFK4FES7NBRTUN X-Message-ID-Hash: HLVNFMRTQ2AB744M6FAFK4FES7NBRTUN X-MailFrom: prvs=3576b45159=rf@opensource.cirrus.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: <> List-Archive: <> List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Only call regcache_mark_dirty() in cs35l56_hda_fw_load() if the CS35L56 was SYSTEM_RESET. recache_mark_dirty() changes the behaviour of regcache_sync() to write out cache values that are not the default value, and skip cache values that are the default. AUDIO_REINIT does not reset the registers. regcache_mark_dirty() after AUDIO_REINIT could cause the regcache_sync() to sync registers incorrectly because it will assume that all registers have reset to default. Signed-off-by: Richard Fitzgerald --- sound/pci/hda/cs35l56_hda.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/hda/cs35l56_hda.c b/sound/pci/hda/cs35l56_hda.c index c3acda2daeeb..fda716e0db09 100644 --- a/sound/pci/hda/cs35l56_hda.c +++ b/sound/pci/hda/cs35l56_hda.c @@ -569,6 +569,7 @@ static int cs35l56_hda_fw_load(struct cs35l56_hda *cs35l56) } else { /* Reset the device and wait for it to boot */ cs35l56_system_reset(&cs35l56->base, false); + regcache_mark_dirty(cs35l56->base.regmap); ret = cs35l56_wait_for_firmware_boot(&cs35l56->base); if (ret) goto err; @@ -579,7 +580,6 @@ static int cs35l56_hda_fw_load(struct cs35l56_hda *cs35l56) if (ret) goto err; - regcache_mark_dirty(cs35l56->base.regmap); regcache_sync(cs35l56->base.regmap); regmap_clear_bits(cs35l56->base.regmap, CS35L56_PROTECTION_STATUS,