| Message ID | 20230823073340.2829821-1-Vijendar.Mukunda@amd.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | aa836152420af94d014ddd677a5f95544abef4f6 |
| Headers | show |
| Series | [1/7] ASoC: SOF: amd: remove unused sha dma interrupt code | expand |
On Wed, 23 Aug 2023 13:03:33 +0530, Vijendar Mukunda wrote: > During initial development time for RN platform, when SHA > dma gets completed, SHA DMA engine used to raise the ACP interrupt. > In ACP interrupt handler, SHA DMA interrupt got handled. > Currently SHA DMA compleition is verified by checking > transfer count using read poll time out logic. > Remove unused SHA dma interrupt handling code. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/7] ASoC: SOF: amd: remove unused sha dma interrupt code commit: aa836152420af94d014ddd677a5f95544abef4f6 [2/7] ASoC: SOF: amd: enable ACP external global interrupt commit: 0a1428141f638fc6fba863de40f0dc7ea91a1d47 [3/7] ASoC: SOF: amd: add module parameter for firmware debug commit: 60eb816ed850b33f5410b1223c5d4d935a6ceb79 [4/7] ASoC: SOF: amd: remove redundant clock mux selection register write commit: f3b2f8b7158026e7a0ab67f5e36c195cdb4c1bf8 [5/7] ASoC: SOF: amd: add conditional check for acp_clkmux_sel register commit: 0d9e4cf5b66e0ffca3d8cf8e9a111d4793877afe [6/7] ASoC: SOF: amd: clear panic mask status when panic occurs commit: 3d02e1c439b4140215b624d423aa3c7554b17a5a [7/7] ASoC: SOF: amd: clear dsp to host interrupt status commit: 38592ae6dc9f84b7a994c43de2136b8115ca30f6 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index b2e00a10a03e..630c2c5fe4c7 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -337,14 +337,7 @@ static irqreturn_t acp_irq_thread(int irq, void *context) { struct snd_sof_dev *sdev = context; const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); - unsigned int val, count = ACP_HW_SEM_RETRY_COUNT; - - val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); - if (val & ACP_SHA_STAT) { - /* Clear SHA interrupt raised by PSP */ - snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, val); - return IRQ_HANDLED; - } + unsigned int count = ACP_HW_SEM_RETRY_COUNT; while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) { /* Wait until acquired HW Semaphore lock or timeout */
During initial development time for RN platform, when SHA dma gets completed, SHA DMA engine used to raise the ACP interrupt. In ACP interrupt handler, SHA DMA interrupt got handled. Currently SHA DMA compleition is verified by checking transfer count using read poll time out logic. Remove unused SHA dma interrupt handling code. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> --- sound/soc/sof/amd/acp.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-)