@@ -735,6 +735,7 @@
#define CS35L41_REVID_B2 0xB2
#define CS35L41_HALO_CORE_RESET 0x00000200
+#define CS35L41_SOFTWARE_RESET 0x5A000000
#define CS35L41_FS1_WINDOW_MASK 0x000007FF
#define CS35L41_FS2_WINDOW_MASK 0x00FFF800
@@ -901,6 +901,9 @@ static int cs35l41_system_resume(struct device *dev)
regcache_cache_only(cs35l41->regmap, false);
+ regmap_write(cs35l41->regmap, CS35L41_SFT_RESET, CS35L41_SOFTWARE_RESET);
+ usleep_range(2000, 2100);
+
ret = cs35l41_wait_boot_done(cs35l41);
if (ret)
return ret;
@@ -1766,6 +1769,8 @@ int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int i
gpiod_set_value_cansleep(cs35l41->reset_gpio, 1);
}
+ usleep_range(2000, 2100);
+ regmap_write(cs35l41->regmap, CS35L41_SFT_RESET, CS35L41_SOFTWARE_RESET);
usleep_range(2000, 2100);
ret = cs35l41_wait_boot_done(cs35l41);
@@ -74,6 +74,7 @@ static bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
case CS35L41_FABID:
case CS35L41_RELID:
case CS35L41_OTPID:
+ case CS35L41_SFT_RESET:
case CS35L41_TEST_KEY_CTL:
case CS35L41_USER_KEY_CTL:
case CS35L41_OTP_CTRL0:
To ensure the chip has correctly reset during probe and system suspend, we need to force a software reset, in case of systems where the hardware reset is not available. The software reset register was labelled as volatile but not readable, however, it is readable, (just returns 0x0). Adding it to readable registers means it will be correctly treated as volatile, and thus will not be cached. Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com> --- include/sound/cs35l41.h | 1 + sound/pci/hda/cs35l41_hda.c | 5 +++++ sound/soc/codecs/cs35l41-lib.c | 1 + 3 files changed, 7 insertions(+)