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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2024 09:25:52.5472 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3022274-a6e8-429a-c2df-08dc1b2c2109 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE35.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5965 Add support for interrupt handling for soundwire manager platform devices. Signed-off-by: Vijendar Mukunda --- sound/soc/sof/amd/acp-dsp-offset.h | 4 ++++ sound/soc/sof/amd/acp.c | 38 +++++++++++++++++++++++++++++- sound/soc/sof/amd/acp.h | 5 ++++ 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/sound/soc/sof/amd/acp-dsp-offset.h b/sound/soc/sof/amd/acp-dsp-offset.h index a913f1cc4c80..7ba6492b8e99 100644 --- a/sound/soc/sof/amd/acp-dsp-offset.h +++ b/sound/soc/sof/amd/acp-dsp-offset.h @@ -78,6 +78,10 @@ #define ACP5X_AXI2DAGB_SEM_0 0x1884 #define ACP6X_AXI2DAGB_SEM_0 0x1874 +/* ACP common registers to report errors related to I2S & SoundWire interfaces */ +#define ACP_SW0_I2S_ERROR_REASON 0x18B4 +#define ACP_SW1_I2S_ERROR_REASON 0x1A50 + /* Registers from ACP_SHA block */ #define ACP_SHA_DSP_FW_QUALIFIER 0x1C70 #define ACP_SHA_DMA_CMD 0x1CB0 diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index f24cd6b7490f..7a34faae9889 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -375,10 +375,13 @@ static irqreturn_t acp_irq_thread(int irq, void *context) static irqreturn_t acp_irq_handler(int irq, void *dev_id) { + struct amd_sdw_manager *amd_manager; struct snd_sof_dev *sdev = dev_id; const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); + struct acp_dev_data *adata = sdev->pdata->hw_pdata; unsigned int base = desc->dsp_intr_base; unsigned int val; + int irq_flag = 0; val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); if (val & ACP_DSP_TO_HOST_IRQ) { @@ -387,7 +390,38 @@ static irqreturn_t acp_irq_handler(int irq, void *dev_id) return IRQ_WAKE_THREAD; } - return IRQ_NONE; + val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); + if (val & ACP_SDW0_IRQ_MASK) { + amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); + if (amd_manager) + schedule_work(&amd_manager->amd_sdw_irq_thread); + irq_flag = 1; + } + + if (val & ACP_ERROR_IRQ_MASK) { + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW0_I2S_ERROR_REASON, 0); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW1_I2S_ERROR_REASON, 0); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_ERROR_STATUS, 0); + irq_flag = 1; + } + + if (desc->ext_intr_stat1) { + val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); + if (val & ACP_SDW1_IRQ_MASK) { + amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, + ACP_SDW1_IRQ_MASK); + if (amd_manager) + schedule_work(&amd_manager->amd_sdw_irq_thread); + irq_flag = 1; + } + } + if (irq_flag) + return IRQ_HANDLED; + else + return IRQ_NONE; } static int acp_power_on(struct snd_sof_dev *sdev) @@ -443,6 +477,8 @@ static int acp_reset(struct snd_sof_dev *sdev) if (desc->ext_intr_enb) snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); + if (desc->ext_intr_cntl) + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); return ret; } diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index e88d01330ec7..2058dae32659 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -93,6 +93,9 @@ #define PROBE_STATUS_BIT BIT(31) #define ACP_FIRMWARE_SIGNATURE 0x100 +#define ACP_ERROR_IRQ_MASK BIT(29) +#define ACP_SDW0_IRQ_MASK BIT(21) +#define ACP_SDW1_IRQ_MASK BIT(2) #define ACP_DEFAULT_SRAM_LENGTH 0x00080000 #define ACP_SRAM_PAGE_COUNT 128 @@ -184,7 +187,9 @@ struct sof_amd_acp_desc { unsigned int host_bridge_id; u32 pgfsm_base; u32 ext_intr_enb; + u32 ext_intr_cntl; u32 ext_intr_stat; + u32 ext_intr_stat1; u32 dsp_intr_base; u32 sram_pte_offset; u32 hw_semaphore_offset;